riscv: refine vector context layout on stack #1329
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Vector general register layout: Before: +--------------+ <-- High Address | v7 | +--------------+ | v6 | +--------------+ | ... | +--------------+ | v0 | +--------------+ <-- v0 - v7 | v15 | +--------------+ | v14 | +--------------+ | ... | +--------------+ | v8 | +--------------+ <-- v8 - v15 | ... | +--------------+ | v24 | +--------------+ <-- Low address After: +--------------+ <-- High Address | v31 | +--------------+ | v30 | +--------------+ | ... | +--------------+ | v1 | +--------------+ | v0 | +--------------+ <-- Low Address Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
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Currently, vector registers are not placed continuously in the stack. Place v31 - v0 in order from high address to low address to facilitate debugger analysis of task stack context.
Vector general register layout:
Before:
+--------------+ <-- High Address
| v7 |
+--------------+
| v6 |
+--------------+
| ... |
+--------------+
| v0 |
+--------------+ <-- v0 - v7
| v15 |
+--------------+
| v14 |
+--------------+
| ... |
+--------------+
| v8 |
+--------------+ <-- v8 - v15
| ... |
+--------------+
| v24 |
+--------------+ <-- Low address
After:
+--------------+ <-- High Address
| v31 |
+--------------+
| v30 |
+--------------+
| ... |
+--------------+
| v1 |
+--------------+
| v0 |
+--------------+ <-- Low Address
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