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chore: more descriptive file rename#691

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KelvinChung2000 wants to merge 5 commits into
FPGA-Research:mainfrom
KelvinChung2000:fix/425-rename-cleanup-cell-libs
Draft

chore: more descriptive file rename#691
KelvinChung2000 wants to merge 5 commits into
FPGA-Research:mainfrom
KelvinChung2000:fix/425-rename-cleanup-cell-libs

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@KelvinChung2000

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This is basically something I did before, but I have done it again to align with the naming that Leo suggested. But this is just a file rename, not the actual module rename, as renaming the module might break a lot of things.

@IAmMarcelJung IAmMarcelJung changed the title chore: more descrpitive file rename chore: more descriptive file rename Apr 17, 2026
@KelvinChung2000 KelvinChung2000 force-pushed the fix/425-rename-cleanup-cell-libs branch 2 times, most recently from dff165c to 53f079f Compare May 8, 2026 22:27
LUT4c_FF -> FABULOUS_LC
wide_frac_MUX -> MUX8
RegFile_32x4 -> RAM_32x4_2R_1W
MULADD -> MACC_8x8_20
IO_1_bi -> IOBUF

Filename-only; module/entity names inside the HDL files are unchanged.
Updates Tile CSVs, VHDL test Makefile, and docs that reference the
filenames.
@KelvinChung2000 KelvinChung2000 force-pushed the fix/425-rename-cleanup-cell-libs branch from 53f079f to 00148bf Compare May 8, 2026 22:28
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