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c29f50b
Failed IC'S
karthikeyan-designs Jul 27, 2025
6549a0a
Added Failed IC'S folder
karthikeyan-designs Jul 27, 2025
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Empty file added library/SubcircuitLibrary/Failed IC'S/.gitkeep
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173 changes: 173 additions & 0 deletions library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC-cache.lib
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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# PORT
#
DEF PORT U 0 40 Y Y 26 F N
F0 "U" 50 100 30 H V C CNN
F1 "PORT" 0 0 30 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
S -100 50 100 -50 0 1 0 N
X ~ 1 250 0 100 L 30 30 1 1 B
X ~ 2 250 0 100 L 30 30 2 1 B
X ~ 3 250 0 100 L 30 30 3 1 B
X ~ 4 250 0 100 L 30 30 4 1 B
X ~ 5 250 0 100 L 30 30 5 1 B
X ~ 6 250 0 100 L 30 30 6 1 B
X ~ 7 250 0 100 L 30 30 7 1 B
X ~ 8 250 0 100 L 30 30 8 1 B
X ~ 9 250 0 100 L 30 30 9 1 B
X ~ 10 250 0 100 L 30 30 10 1 B
X ~ 11 250 0 100 L 30 30 11 1 B
X ~ 12 250 0 100 L 30 30 12 1 B
X ~ 13 250 0 100 L 30 30 13 1 B
X ~ 14 250 0 100 L 30 30 14 1 B
X ~ 15 250 0 100 L 30 30 15 1 B
X ~ 16 250 0 100 L 30 30 16 1 B
X ~ 17 250 0 100 L 30 30 17 1 B
X ~ 18 250 0 100 L 30 30 18 1 B
X ~ 19 250 0 100 L 30 30 19 1 B
X ~ 20 250 0 100 L 30 30 20 1 B
X ~ 21 250 0 100 L 30 30 21 1 B
X ~ 22 250 0 100 L 30 30 22 1 B
X ~ 23 250 0 100 L 30 30 23 1 B
X ~ 24 250 0 100 L 30 30 24 1 B
X ~ 25 250 0 100 L 30 30 25 1 B
X ~ 26 250 0 100 L 30 30 26 1 B
ENDDRAW
ENDDEF
#
# adc_bridge_1
#
DEF adc_bridge_1 U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "adc_bridge_1" 0 150 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -400 200 350 -50 0 1 0 N
X IN1 1 -600 50 200 R 50 50 1 1 I
X OUT1 2 550 50 200 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# adc_bridge_2
#
DEF adc_bridge_2 U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "adc_bridge_2" 0 150 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -400 200 350 -100 0 1 0 N
X IN1 1 -600 50 200 R 50 50 1 1 I
X IN2 2 -600 -50 200 R 50 50 1 1 I
X OUT1 3 550 50 200 L 50 50 1 1 O
X OUT2 4 550 -50 200 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# d_inverter
#
DEF d_inverter U 0 40 Y Y 1 F N
F0 "U" 0 -100 60 H V C CNN
F1 "d_inverter" 0 150 60 H V C CNN
F2 "" 50 -50 60 H V C CNN
F3 "" 50 -50 60 H V C CNN
DRAW
P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
X ~ 1 -300 0 200 R 50 50 1 1 I
X ~ 2 300 0 200 L 50 50 1 1 O I
ENDDRAW
ENDDEF
#
# d_tristate
#
DEF d_tristate U 0 40 Y Y 1 F N
F0 "U" -250 250 60 H V C CNN
F1 "d_tristate" -200 450 60 H V C CNN
F2 "" -100 350 60 H V C CNN
F3 "" -100 350 60 H V C CNN
DRAW
P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N
X IN 1 -600 350 200 R 50 50 1 1 I
X EN 2 -50 50 193 U 50 50 1 1 I
X OUT 3 550 350 200 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# dac_bridge_1
#
DEF dac_bridge_1 U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "dac_bridge_1" 0 150 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -400 200 350 -50 0 1 0 N
X IN1 1 -600 50 200 R 50 50 1 1 I
X OUT1 2 550 50 200 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# eSim_MOS_N
#
DEF eSim_MOS_N M 0 0 Y N 1 F N
F0 "M" 0 -150 50 H V R CNN
F1 "eSim_MOS_N" 100 -50 50 H V R CNN
F2 "" 300 -300 29 H V C CNN
F3 "" 100 -200 60 H V C CNN
ALIAS mosfet_n
DRAW
C 150 -200 111 0 1 10 N
P 2 0 1 10 130 -290 130 -250 N
P 2 0 1 0 130 -270 200 -270 N
P 2 0 1 10 130 -220 130 -180 N
P 2 0 1 0 130 -200 200 -200 N
P 2 0 1 10 130 -150 130 -110 N
P 2 0 1 0 130 -130 200 -130 N
P 2 0 1 0 200 -300 200 -270 N
P 2 0 1 0 200 -130 200 -100 N
P 3 0 1 10 110 -275 110 -125 110 -125 N
P 3 0 1 0 200 -200 300 -200 300 -250 N
P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
X D 1 200 0 100 D 50 50 1 1 P
X G 2 -100 -200 210 R 50 50 1 1 P
X S 3 200 -400 100 U 50 50 1 1 P
X B 4 300 -350 98 U 47 47 1 1 P
ENDDRAW
ENDDEF
#
# eSim_MOS_P
#
DEF eSim_MOS_P M 0 0 Y N 1 F N
F0 "M" -50 50 50 H V R CNN
F1 "eSim_MOS_P" 50 150 50 H V R CNN
F2 "" 250 100 29 H V C CNN
F3 "" 50 0 60 H V C CNN
ALIAS mosfet_p
DRAW
C 100 0 111 0 1 10 N
P 2 0 1 0 80 -70 150 -70 N
P 2 0 1 10 80 -50 80 -90 N
P 2 0 1 0 80 0 150 0 N
P 2 0 1 10 80 20 80 -20 N
P 2 0 1 0 80 70 150 70 N
P 2 0 1 10 80 90 80 50 N
P 2 0 1 0 150 -70 150 -100 N
P 2 0 1 0 150 100 150 70 N
P 3 0 1 10 60 75 60 -75 60 -75 N
P 3 0 1 0 150 0 250 0 250 -50 N
P 4 0 1 0 140 0 100 -15 100 15 140 0 F
X D 1 150 200 100 D 50 50 1 1 P
X G 2 -150 0 210 R 50 50 1 1 P
X S 3 150 -200 100 U 50 50 1 1 P
X B 4 250 -150 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library
40 changes: 40 additions & 0 deletions library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.cir
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* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4024BC\CD4024BC.cir

* EESchema Netlist Version 1.1 (Spice format) creation date: 06/19/25 23:21:47

* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0

* Sheet Name: /
U2 Net-_U12-Pad3_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_tristate
M2 Net-_M1-Pad3_ Net-_M2-Pad2_ Net-_M1-Pad1_ vdd eSim_MOS_P
M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ gnd eSim_MOS_N
M4 Net-_M3-Pad3_ Net-_M2-Pad2_ Net-_M1-Pad3_ vdd eSim_MOS_P
M3 Net-_M1-Pad3_ Net-_M1-Pad2_ Net-_M3-Pad3_ gnd eSim_MOS_N
M5 Net-_M5-Pad1_ Net-_M2-Pad2_ Net-_M5-Pad3_ vdd eSim_MOS_P
M6 Net-_M5-Pad3_ Net-_M5-Pad3_ Net-_M5-Pad1_ gnd eSim_MOS_N
M8 Net-_M7-Pad3_ Net-_M5-Pad3_ Net-_M5-Pad3_ gnd eSim_MOS_N
M7 Net-_M5-Pad3_ Net-_M2-Pad2_ Net-_M7-Pad3_ vdd eSim_MOS_P
U3 Net-_U15-Pad1_ Net-_U22-Pad2_ Net-_U14-Pad1_ d_tristate
U4 Net-_U17-Pad2_ Net-_U22-Pad2_ Net-_U10-Pad1_ d_tristate
U1 vdd gnd Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_M1-Pad1_ Net-_U1-Pad7_ PORT
U7 Net-_U2-Pad3_ Net-_M1-Pad2_ d_inverter
U8 Net-_U5-Pad2_ Net-_U2-Pad2_ d_inverter
U5 Net-_U12-Pad4_ Net-_U5-Pad2_ d_inverter
U9 Net-_M1-Pad2_ Net-_U18-Pad1_ d_inverter
U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter
U11 Net-_U10-Pad1_ Net-_U11-Pad2_ d_inverter
U6 Net-_U13-Pad2_ Net-_U15-Pad1_ d_inverter
U18 Net-_U18-Pad1_ Net-_M2-Pad2_ dac_bridge_1
U19 Net-_M1-Pad2_ Net-_M5-Pad3_ dac_bridge_1
U14 Net-_U14-Pad1_ Net-_M3-Pad3_ dac_bridge_1
U13 Net-_M1-Pad3_ Net-_U13-Pad2_ adc_bridge_1
U15 Net-_U15-Pad1_ Net-_M5-Pad1_ dac_bridge_1
U17 Net-_M5-Pad3_ Net-_U17-Pad2_ adc_bridge_1
U16 Net-_U10-Pad2_ Net-_M7-Pad3_ dac_bridge_1
U21 Net-_U11-Pad2_ Net-_U1-Pad5_ dac_bridge_1
U12 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U12-Pad3_ Net-_U12-Pad4_ adc_bridge_2
U20 Net-_U10-Pad1_ Net-_U1-Pad7_ adc_bridge_1
U22 Net-_U2-Pad2_ Net-_U22-Pad2_ dac_bridge_1

.end
106 changes: 106 additions & 0 deletions library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.cir.out
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* c:\fossee\esim\library\subcircuitlibrary\cd4024bc\cd4024bc.cir

.include PMOS-180nm.lib
.include NMOS-180nm.lib
* u2 net-_u12-pad3_ net-_u2-pad2_ net-_u2-pad3_ d_tristate
m2 net-_m1-pad3_ net-_m2-pad2_ net-_m1-pad1_ vdd CMOSP W=100u L=100u M=1
m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
m4 net-_m3-pad3_ net-_m2-pad2_ net-_m1-pad3_ vdd CMOSP W=100u L=100u M=1
m3 net-_m1-pad3_ net-_m1-pad2_ net-_m3-pad3_ gnd CMOSN W=100u L=100u M=1
m5 net-_m5-pad1_ net-_m2-pad2_ net-_m5-pad3_ vdd CMOSP W=100u L=100u M=1
m6 net-_m5-pad3_ net-_m5-pad3_ net-_m5-pad1_ gnd CMOSN W=100u L=100u M=1
m8 net-_m7-pad3_ net-_m5-pad3_ net-_m5-pad3_ gnd CMOSN W=100u L=100u M=1
m7 net-_m5-pad3_ net-_m2-pad2_ net-_m7-pad3_ vdd CMOSP W=100u L=100u M=1
* u3 net-_u15-pad1_ net-_u22-pad2_ net-_u14-pad1_ d_tristate
* u4 net-_u17-pad2_ net-_u22-pad2_ net-_u10-pad1_ d_tristate
* u1 vdd gnd net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_m1-pad1_ net-_u1-pad7_ port
* u7 net-_u2-pad3_ net-_m1-pad2_ d_inverter
* u8 net-_u5-pad2_ net-_u2-pad2_ d_inverter
* u5 net-_u12-pad4_ net-_u5-pad2_ d_inverter
* u9 net-_m1-pad2_ net-_u18-pad1_ d_inverter
* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
* u11 net-_u10-pad1_ net-_u11-pad2_ d_inverter
* u6 net-_u13-pad2_ net-_u15-pad1_ d_inverter
* u18 net-_u18-pad1_ net-_m2-pad2_ dac_bridge_1
* u19 net-_m1-pad2_ net-_m5-pad3_ dac_bridge_1
* u14 net-_u14-pad1_ net-_m3-pad3_ dac_bridge_1
* u13 net-_m1-pad3_ net-_u13-pad2_ adc_bridge_1
* u15 net-_u15-pad1_ net-_m5-pad1_ dac_bridge_1
* u17 net-_m5-pad3_ net-_u17-pad2_ adc_bridge_1
* u16 net-_u10-pad2_ net-_m7-pad3_ dac_bridge_1
* u21 net-_u11-pad2_ net-_u1-pad5_ dac_bridge_1
* u12 net-_u1-pad3_ net-_u1-pad4_ net-_u12-pad3_ net-_u12-pad4_ adc_bridge_2
* u20 net-_u10-pad1_ net-_u1-pad7_ adc_bridge_1
* u22 net-_u2-pad2_ net-_u22-pad2_ dac_bridge_1
a1 net-_u12-pad3_ net-_u2-pad2_ net-_u2-pad3_ u2
a2 net-_u15-pad1_ net-_u22-pad2_ net-_u14-pad1_ u3
a3 net-_u17-pad2_ net-_u22-pad2_ net-_u10-pad1_ u4
a4 net-_u2-pad3_ net-_m1-pad2_ u7
a5 net-_u5-pad2_ net-_u2-pad2_ u8
a6 net-_u12-pad4_ net-_u5-pad2_ u5
a7 net-_m1-pad2_ net-_u18-pad1_ u9
a8 net-_u10-pad1_ net-_u10-pad2_ u10
a9 net-_u10-pad1_ net-_u11-pad2_ u11
a10 net-_u13-pad2_ net-_u15-pad1_ u6
a11 [net-_u18-pad1_ ] [net-_m2-pad2_ ] u18
a12 [net-_m1-pad2_ ] [net-_m5-pad3_ ] u19
a13 [net-_u14-pad1_ ] [net-_m3-pad3_ ] u14
a14 [net-_m1-pad3_ ] [net-_u13-pad2_ ] u13
a15 [net-_u15-pad1_ ] [net-_m5-pad1_ ] u15
a16 [net-_m5-pad3_ ] [net-_u17-pad2_ ] u17
a17 [net-_u10-pad2_ ] [net-_m7-pad3_ ] u16
a18 [net-_u11-pad2_ ] [net-_u1-pad5_ ] u21
a19 [net-_u1-pad3_ net-_u1-pad4_ ] [net-_u12-pad3_ net-_u12-pad4_ ] u12
a20 [net-_u10-pad1_ ] [net-_u1-pad7_ ] u20
a21 [net-_u2-pad2_ ] [net-_u22-pad2_ ] u22
* Schematic Name: d_tristate, NgSpice Name: d_tristate
.model u2 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
* Schematic Name: d_tristate, NgSpice Name: d_tristate
.model u3 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
* Schematic Name: d_tristate, NgSpice Name: d_tristate
.model u4 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
.model u18 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
.model u19 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
.model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
.model u13 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
.model u15 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
.model u17 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
.model u21 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge
.model u12 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
.model u20 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
.tran 0e-00 0e-00 0e-00

* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end
73 changes: 73 additions & 0 deletions library/SubcircuitLibrary/Failed IC'S/CD4024BC/CD4024BC.pro
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update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=adc-dac
LibName2=memory
LibName3=xilinx
LibName4=microcontrollers
LibName5=dsp
LibName6=microchip
LibName7=analog_switches
LibName8=motorola
LibName9=texas
LibName10=intel
LibName11=audio
LibName12=interface
LibName13=digital-audio
LibName14=philips
LibName15=display
LibName16=cypress
LibName17=siliconi
LibName18=opto
LibName19=atmel
LibName20=contrib
LibName21=power
LibName22=eSim_Plot
LibName23=transistors
LibName24=conn
LibName25=eSim_User
LibName26=regul
LibName27=74xx
LibName28=cmos4000
LibName29=eSim_Analog
LibName30=eSim_Devices
LibName31=eSim_Digital
LibName32=eSim_Hybrid
LibName33=eSim_Miscellaneous
LibName34=eSim_Power
LibName35=eSim_Sources
LibName36=eSim_Subckt
LibName37=eSim_Nghdl
LibName38=eSim_Ngveri
LibName39=eSim_SKY130
LibName40=eSim_SKY130_Subckts
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