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miguelangelo78miguelangelo78
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Added generic UART module
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11 files changed

+851
-179
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11 files changed

+851
-179
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‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/fisc_core.bsf‎

Lines changed: 90 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -21,9 +21,9 @@ agreement for further details.
2121
*/
2222
(header "symbol" (version "1.1"))
2323
(symbol
24-
(rect 16 16 256 320)
24+
(rect 16 16 264 352)
2525
(text "FISC_Core" (rect 5 0 52 12)(font "Arial" ))
26-
(text "inst" (rect 8 288 20 300)(font "Arial" ))
26+
(text "inst" (rect 8 320 20 332)(font "Arial" ))
2727
(port
2828
(pt 0 32)
2929
(input)
@@ -74,111 +74,153 @@ agreement for further details.
7474
(line (pt 0 128)(pt 16 128)(line_width 3))
7575
)
7676
(port
77-
(pt 240 32)
77+
(pt 0 144)
78+
(input)
79+
(text "dbg_uart_dout[7..0]" (rect 0 0 77 12)(font "Arial" ))
80+
(text "dbg_uart_dout[7..0]" (rect 21 139 98 151)(font "Arial" ))
81+
(line (pt 0 144)(pt 16 144)(line_width 3))
82+
)
83+
(port
84+
(pt 0 160)
85+
(input)
86+
(text "dbg_uart_tx_busy" (rect 0 0 74 12)(font "Arial" ))
87+
(text "dbg_uart_tx_busy" (rect 21 155 95 167)(font "Arial" ))
88+
(line (pt 0 160)(pt 16 160)(line_width 1))
89+
)
90+
(port
91+
(pt 0 176)
92+
(input)
93+
(text "dbg_uart_rdy" (rect 0 0 55 12)(font "Arial" ))
94+
(text "dbg_uart_rdy" (rect 21 171 76 183)(font "Arial" ))
95+
(line (pt 0 176)(pt 16 176)(line_width 1))
96+
)
97+
(port
98+
(pt 248 32)
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(output)
79100
(text "halt_n" (rect 0 0 23 12)(font "Arial" ))
80-
(text "halt_n" (rect 196 27 219 39)(font "Arial" ))
81-
(line (pt 240 32)(pt 224 32)(line_width 1))
101+
(text "halt_n" (rect 204 27 227 39)(font "Arial" ))
102+
(line (pt 248 32)(pt 232 32)(line_width 1))
82103
)
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(port
84-
(pt 240 48)
105+
(pt 248 48)
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(output)
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(text "ioack_n" (rect 0 0 30 12)(font "Arial" ))
87-
(text "ioack_n" (rect 189 43 219 55)(font "Arial" ))
88-
(line (pt 240 48)(pt 224 48)(line_width 1))
108+
(text "ioack_n" (rect 197 43 227 55)(font "Arial" ))
109+
(line (pt 248 48)(pt 232 48)(line_width 1))
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)
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(port
91-
(pt 240 64)
112+
(pt 248 64)
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(output)
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(text "wr_a" (rect 0 0 20 12)(font "Arial" ))
94-
(text "wr_a" (rect 199 59 219 71)(font "Arial" ))
95-
(line (pt 240 64)(pt 224 64)(line_width 1))
115+
(text "wr_a" (rect 207 59 227 71)(font "Arial" ))
116+
(line (pt 248 64)(pt 232 64)(line_width 1))
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)
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(port
98-
(pt 240 80)
119+
(pt 248 80)
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(output)
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(text "rd_a" (rect 0 0 18 12)(font "Arial" ))
101-
(text "rd_a" (rect 201 75 219 87)(font "Arial" ))
102-
(line (pt 240 80)(pt 224 80)(line_width 1))
122+
(text "rd_a" (rect 209 75 227 87)(font "Arial" ))
123+
(line (pt 248 80)(pt 232 80)(line_width 1))
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)
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(port
105-
(pt 240 96)
126+
(pt 248 96)
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(output)
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(text "wr_b" (rect 0 0 20 12)(font "Arial" ))
108-
(text "wr_b" (rect 199 91 219 103)(font "Arial" ))
109-
(line (pt 240 96)(pt 224 96)(line_width 1))
129+
(text "wr_b" (rect 207 91 227 103)(font "Arial" ))
130+
(line (pt 248 96)(pt 232 96)(line_width 1))
110131
)
111132
(port
112-
(pt 240 112)
133+
(pt 248 112)
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(output)
114135
(text "rd_b" (rect 0 0 18 12)(font "Arial" ))
115-
(text "rd_b" (rect 201 107 219 119)(font "Arial" ))
116-
(line (pt 240 112)(pt 224 112)(line_width 1))
136+
(text "rd_b" (rect 209 107 227 119)(font "Arial" ))
137+
(line (pt 248 112)(pt 232 112)(line_width 1))
117138
)
118139
(port
119-
(pt 240 128)
140+
(pt 248 128)
120141
(output)
121142
(text "dout_bus_a[63..0]" (rect 0 0 71 12)(font "Arial" ))
122-
(text "dout_bus_a[63..0]" (rect 148 123 219 135)(font "Arial" ))
123-
(line (pt 240 128)(pt 224 128)(line_width 3))
143+
(text "dout_bus_a[63..0]" (rect 156 123 227 135)(font "Arial" ))
144+
(line (pt 248 128)(pt 232 128)(line_width 3))
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)
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(port
126-
(pt 240 144)
147+
(pt 248 144)
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(output)
128149
(text "addr_bus_a[10..0]" (rect 0 0 71 12)(font "Arial" ))
129-
(text "addr_bus_a[10..0]" (rect 148 139 219 151)(font "Arial" ))
130-
(line (pt 240 144)(pt 224 144)(line_width 3))
150+
(text "addr_bus_a[10..0]" (rect 156 139 227 151)(font "Arial" ))
151+
(line (pt 248 144)(pt 232 144)(line_width 3))
131152
)
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(port
133-
(pt 240 160)
154+
(pt 248 160)
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(output)
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(text "dout_bus_b[63..0]" (rect 0 0 71 12)(font "Arial" ))
136-
(text "dout_bus_b[63..0]" (rect 148 155 219 167)(font "Arial" ))
137-
(line (pt 240 160)(pt 224 160)(line_width 3))
157+
(text "dout_bus_b[63..0]" (rect 156 155 227 167)(font "Arial" ))
158+
(line (pt 248 160)(pt 232 160)(line_width 3))
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)
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(port
140-
(pt 240 176)
161+
(pt 248 176)
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(output)
142163
(text "addr_bus_b[10..0]" (rect 0 0 71 12)(font "Arial" ))
143-
(text "addr_bus_b[10..0]" (rect 148 171 219 183)(font "Arial" ))
144-
(line (pt 240 176)(pt 224 176)(line_width 3))
164+
(text "addr_bus_b[10..0]" (rect 156 171 227 183)(font "Arial" ))
165+
(line (pt 248 176)(pt 232 176)(line_width 3))
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)
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(port
147-
(pt 240 192)
168+
(pt 248 192)
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(output)
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(text "dbg_init" (rect 0 0 29 12)(font "Arial" ))
150-
(text "dbg_init" (rect 190 187 219 199)(font "Arial" ))
151-
(line (pt 240 192)(pt 224 192)(line_width 1))
171+
(text "dbg_init" (rect 198 187 227 199)(font "Arial" ))
172+
(line (pt 248 192)(pt 232 192)(line_width 1))
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)
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(port
154-
(pt 240 208)
175+
(pt 248 208)
155176
(output)
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(text "dbg1[3..0]" (rect 0 0 37 12)(font "Arial" ))
157-
(text "dbg1[3..0]" (rect 182 203 219 215)(font "Arial" ))
158-
(line (pt 240 208)(pt 224 208)(line_width 3))
178+
(text "dbg1[3..0]" (rect 190 203 227 215)(font "Arial" ))
179+
(line (pt 248 208)(pt 232 208)(line_width 3))
159180
)
160181
(port
161-
(pt 240 224)
182+
(pt 248 224)
162183
(output)
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(text "dbg2[3..0]" (rect 0 0 38 12)(font "Arial" ))
164-
(text "dbg2[3..0]" (rect 181 219 219 231)(font "Arial" ))
165-
(line (pt 240 224)(pt 224 224)(line_width 3))
185+
(text "dbg2[3..0]" (rect 189 219 227 231)(font "Arial" ))
186+
(line (pt 248 224)(pt 232 224)(line_width 3))
166187
)
167188
(port
168-
(pt 240 240)
189+
(pt 248 240)
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(output)
170191
(text "dbg3[3..0]" (rect 0 0 38 12)(font "Arial" ))
171-
(text "dbg3[3..0]" (rect 181 235 219 247)(font "Arial" ))
172-
(line (pt 240 240)(pt 224 240)(line_width 3))
192+
(text "dbg3[3..0]" (rect 189 235 227 247)(font "Arial" ))
193+
(line (pt 248 240)(pt 232 240)(line_width 3))
173194
)
174195
(port
175-
(pt 240 256)
196+
(pt 248 256)
176197
(output)
177198
(text "dbg4[3..0]" (rect 0 0 40 12)(font "Arial" ))
178-
(text "dbg4[3..0]" (rect 179 251 219 263)(font "Arial" ))
179-
(line (pt 240 256)(pt 224 256)(line_width 3))
199+
(text "dbg4[3..0]" (rect 187 251 227 263)(font "Arial" ))
200+
(line (pt 248 256)(pt 232 256)(line_width 3))
201+
)
202+
(port
203+
(pt 248 272)
204+
(output)
205+
(text "dbg_uart_din[7..0]" (rect 0 0 71 12)(font "Arial" ))
206+
(text "dbg_uart_din[7..0]" (rect 156 267 227 279)(font "Arial" ))
207+
(line (pt 248 272)(pt 232 272)(line_width 3))
208+
)
209+
(port
210+
(pt 248 288)
211+
(output)
212+
(text "dbg_uart_wr_en" (rect 0 0 66 12)(font "Arial" ))
213+
(text "dbg_uart_wr_en" (rect 161 283 227 295)(font "Arial" ))
214+
(line (pt 248 288)(pt 232 288)(line_width 1))
215+
)
216+
(port
217+
(pt 248 304)
218+
(output)
219+
(text "dbg_uart_rdy_clr" (rect 0 0 70 12)(font "Arial" ))
220+
(text "dbg_uart_rdy_clr" (rect 157 299 227 311)(font "Arial" ))
221+
(line (pt 248 304)(pt 232 304)(line_width 1))
180222
)
181223
(drawing
182-
(rectangle (rect 16 16 224 288)(line_width 1))
224+
(rectangle (rect 16 16 232 320)(line_width 1))
183225
)
184226
)

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/top.qsf‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -172,6 +172,8 @@ set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR ../../simulation/model
172172
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
173173
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
174174
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS ON
175+
set_global_assignment -name SYSTEMVERILOG_FILE ../../rtl/uart/uart.sv
176+
set_global_assignment -name SYSTEMVERILOG_FILE ../../rtl/seven_segment.sv
175177
set_global_assignment -name HEX_FILE ../../bin/onchip_mem.hex
176178
set_global_assignment -name SYSTEMVERILOG_FILE ../../rtl/fisc_core/fisc_core.sv
177179
set_global_assignment -name BDF_FILE ../../rtl/top.bdf

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/top.qws‎

-1.85 KB
Binary file not shown.

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/uart.bsf‎

Lines changed: 93 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,93 @@
1+
/*
2+
WARNING: Do NOT edit the input and output ports in this file in a text
3+
editor if you plan to continue editing the block that represents it in
4+
the Block Editor! File corruption is VERY likely to occur.
5+
*/
6+
/*
7+
Copyright (C) 2017 Intel Corporation. All rights reserved.
8+
Your use of Intel Corporation's design tools, logic functions
9+
and other software and tools, and its AMPP partner logic
10+
functions, and any output files from any of the foregoing
11+
(including device programming or simulation files), and any
12+
associated documentation or information are expressly subject
13+
to the terms and conditions of the Intel Program License
14+
Subscription Agreement, the Intel Quartus Prime License Agreement,
15+
the Intel MegaCore Function License Agreement, or other
16+
applicable license agreement, including, without limitation,
17+
that your use is for the sole purpose of programming logic
18+
devices manufactured by Intel and sold by Intel or its
19+
authorized distributors. Please refer to the applicable
20+
agreement for further details.
21+
*/
22+
(header "symbol" (version "1.1"))
23+
(symbol
24+
(rect 16 16 192 160)
25+
(text "uart" (rect 5 0 20 12)(font "Arial" ))
26+
(text "inst" (rect 8 128 20 140)(font "Arial" ))
27+
(port
28+
(pt 0 32)
29+
(input)
30+
(text "din[7..0]" (rect 0 0 30 12)(font "Arial" ))
31+
(text "din[7..0]" (rect 21 27 51 39)(font "Arial" ))
32+
(line (pt 0 32)(pt 16 32)(line_width 3))
33+
)
34+
(port
35+
(pt 0 48)
36+
(input)
37+
(text "clk_50m" (rect 0 0 34 12)(font "Arial" ))
38+
(text "clk_50m" (rect 21 43 55 55)(font "Arial" ))
39+
(line (pt 0 48)(pt 16 48)(line_width 1))
40+
)
41+
(port
42+
(pt 0 64)
43+
(input)
44+
(text "wr_en" (rect 0 0 24 12)(font "Arial" ))
45+
(text "wr_en" (rect 21 59 45 71)(font "Arial" ))
46+
(line (pt 0 64)(pt 16 64)(line_width 1))
47+
)
48+
(port
49+
(pt 0 80)
50+
(input)
51+
(text "rx" (rect 0 0 8 12)(font "Arial" ))
52+
(text "rx" (rect 21 75 29 87)(font "Arial" ))
53+
(line (pt 0 80)(pt 16 80)(line_width 1))
54+
)
55+
(port
56+
(pt 0 96)
57+
(input)
58+
(text "rdy_clr" (rect 0 0 29 12)(font "Arial" ))
59+
(text "rdy_clr" (rect 21 91 50 103)(font "Arial" ))
60+
(line (pt 0 96)(pt 16 96)(line_width 1))
61+
)
62+
(port
63+
(pt 176 32)
64+
(output)
65+
(text "dout[7..0]" (rect 0 0 36 12)(font "Arial" ))
66+
(text "dout[7..0]" (rect 119 27 155 39)(font "Arial" ))
67+
(line (pt 176 32)(pt 160 32)(line_width 3))
68+
)
69+
(port
70+
(pt 176 48)
71+
(output)
72+
(text "tx" (rect 0 0 7 12)(font "Arial" ))
73+
(text "tx" (rect 148 43 155 55)(font "Arial" ))
74+
(line (pt 176 48)(pt 160 48)(line_width 1))
75+
)
76+
(port
77+
(pt 176 64)
78+
(output)
79+
(text "tx_busy" (rect 0 0 33 12)(font "Arial" ))
80+
(text "tx_busy" (rect 122 59 155 71)(font "Arial" ))
81+
(line (pt 176 64)(pt 160 64)(line_width 1))
82+
)
83+
(port
84+
(pt 176 80)
85+
(output)
86+
(text "rdy" (rect 0 0 14 12)(font "Arial" ))
87+
(text "rdy" (rect 141 75 155 87)(font "Arial" ))
88+
(line (pt 176 80)(pt 160 80)(line_width 1))
89+
)
90+
(drawing
91+
(rectangle (rect 16 16 160 128)(line_width 1))
92+
)
93+
)

‎rtl/fisc_core/debug.sv‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,33 @@ task debug(bit[15:0] value);
3333
dbg_regs[3] <= value[15:12];
3434
endtask
3535

36+
task debug_uart_tx(bit[7:0] data);
37+
dbg_uart_din <= data;
38+
dbg_uart_wr_en <= 1;
39+
endtask
40+
41+
task debug_uart_tx_stop;
42+
dbg_uart_wr_en <= 0;
43+
endtask
44+
45+
function [7:0] debug_uart_rx;
46+
/* TODO */
47+
endfunction
48+
49+
task debug_uart_rx_stop;
50+
dbg_uart_rdy_clr <= 0;
51+
endtask
52+
53+
task debug_uart_stop;
54+
debug_uart_tx_stop();
55+
debug_uart_rx_stop();
56+
endtask
57+
3658
task debugInit;
59+
/* Initialize 7 segment display */
3760
debug('hFFFF);
61+
62+
/* Initialize UART wires */
63+
dbg_uart_din <= 0;
64+
debug_uart_stop();
3865
endtask

‎rtl/fisc_core/fisc_core.sv‎

Lines changed: 18 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -24,13 +24,20 @@ module FISC_Core(
2424
input [`FISC_INTEGER_SZ-1:0] din_bus_b, /* Data Input Bus (channel b) */
2525
output reg [`FISC_INTEGER_SZ-1:0] dout_bus_b, /* Data Output Bus (channel b) */
2626
output reg [`FISC_ADDRESS_BOOT_SZ-1:0] addr_bus_b, /* Address Bus (channel b) */
27-
27+
2828
/* Debug wires */
2929
output dbg_init,
3030
output [3:0] dbg1,
3131
output [3:0] dbg2,
3232
output [3:0] dbg3,
33-
output [3:0] dbg4
33+
output [3:0] dbg4,
34+
/* Debug UART wires */
35+
output reg [7:0] dbg_uart_din,
36+
input [7:0] dbg_uart_dout,
37+
output reg dbg_uart_wr_en,
38+
input dbg_uart_tx_busy,
39+
input dbg_uart_rdy,
40+
output reg dbg_uart_rdy_clr
3441
);
3542

3643
`include "debug.sv"
@@ -148,6 +155,9 @@ module FISC_Core(
148155
wr_fromimm = 0;
149156
wr_fromreg = 0;
150157

158+
/* Debug UART */
159+
debug_uart_stop();
160+
151161
fetch_word_tophalf <= 0;
152162
ctr <= 0;
153163
endtask
@@ -215,9 +225,13 @@ module FISC_Core(
215225
if(!initialized)
216226
debugInit();
217227

218-
if(!wait_n)
228+
if(!wait_n) begin
219229
ctr <= 0;
220-
230+
debug_uart_tx(109);
231+
end else begin
232+
debug_uart_tx_stop();
233+
end
234+
221235
if(!reset_n) begin
222236
/* Trigger reset cycle */
223237
cpu_state <= ST_COLDSTART;

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