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miguelangelo78miguelangelo78
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Added 7seg. display, debugging functions and onchip ram
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‎bin/.gitignore‎

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/*
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!.gitignore

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/fisc_core.bsf‎

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@@ -21,9 +21,9 @@ agreement for further details.
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*/
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(header "symbol" (version "1.1"))
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(symbol
24-
(rect 16 16 192 192)
25-
(text "fisc_core" (rect 5 0 42 12)(font "Arial" ))
26-
(text "inst" (rect 8 160 20 172)(font "Arial" ))
24+
(rect 16 16 256 320)
25+
(text "FISC_Core" (rect 5 0 52 12)(font "Arial" ))
26+
(text "inst" (rect 8 288 20 300)(font "Arial" ))
2727
(port
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(pt 0 32)
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(input)
@@ -60,55 +60,125 @@ agreement for further details.
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(line (pt 0 96)(pt 16 96)(line_width 1))
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)
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(port
63-
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63+
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(input)
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(text "din_bus_a[63..0]" (rect 0 0 66 12)(font "Arial" ))
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(text "din_bus_a[63..0]" (rect 21 107 87 119)(font "Arial" ))
67+
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(port
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(pt 0 128)
71+
(input)
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(text "din_bus_b[63..0]" (rect 0 0 66 12)(font "Arial" ))
73+
(text "din_bus_b[63..0]" (rect 21 123 87 135)(font "Arial" ))
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(line (pt 0 128)(pt 16 128)(line_width 3))
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)
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(port
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(pt 240 32)
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(output)
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(text "halt_n" (rect 0 0 23 12)(font "Arial" ))
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67-
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(text "halt_n" (rect 196 27 219 39)(font "Arial" ))
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(line (pt 240 32)(pt 224 32)(line_width 1))
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)
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(port
70-
(pt 176 48)
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(pt 240 48)
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(output)
72-
(text "opcycle_n" (rect 0 0 41 12)(font "Arial" ))
73-
(text "opcycle_n" (rect 114 43 155 55)(font "Arial" ))
74-
(line (pt 176 48)(pt 160 48)(line_width 1))
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(text "ioack_n" (rect 0 0 30 12)(font "Arial" ))
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(text "ioack_n" (rect 189 43 219 55)(font "Arial" ))
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(line (pt 240 48)(pt 224 48)(line_width 1))
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(port
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(output)
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(text "ioack_n" (rect 125 59 155 71)(font "Arial" ))
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(line (pt 176 64)(pt 160 64)(line_width 1))
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(text "wr_a" (rect 0 0 20 12)(font "Arial" ))
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(text "wr_a" (rect 199 59 219 71)(font "Arial" ))
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(line (pt 240 64)(pt 224 64)(line_width 1))
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(port
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(pt 240 80)
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(text "rd_a" (rect 0 0 18 12)(font "Arial" ))
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(text "rd_a" (rect 201 75 219 87)(font "Arial" ))
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(line (pt 240 80)(pt 224 80)(line_width 1))
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(text "wr_b" (rect 199 91 219 103)(font "Arial" ))
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(port
84-
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(output)
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(text "wr_n" (rect 135 75 155 87)(font "Arial" ))
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121+
(text "dout_bus_a[63..0]" (rect 0 0 71 12)(font "Arial" ))
122+
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(port
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(output)
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129+
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(line (pt 176 128)(pt 160 128)(line_width 3))
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(line (pt 240 192)(pt 224 192)(line_width 1))
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)
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(pt 240 208)
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(output)
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(text "dbg1[3..0]" (rect 0 0 37 12)(font "Arial" ))
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(text "dbg1[3..0]" (rect 182 203 219 215)(font "Arial" ))
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(line (pt 240 208)(pt 224 208)(line_width 3))
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(pt 240 224)
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(text "dbg2[3..0]" (rect 0 0 38 12)(font "Arial" ))
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(text "dbg2[3..0]" (rect 181 219 219 231)(font "Arial" ))
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)
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(port
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(pt 240 240)
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(output)
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(text "dbg3[3..0]" (rect 0 0 38 12)(font "Arial" ))
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(text "dbg3[3..0]" (rect 181 235 219 247)(font "Arial" ))
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(line (pt 240 240)(pt 224 240)(line_width 3))
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)
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(port
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(pt 240 256)
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(output)
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(text "dbg4[3..0]" (rect 0 0 40 12)(font "Arial" ))
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(text "dbg4[3..0]" (rect 179 251 219 263)(font "Arial" ))
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(line (pt 240 256)(pt 224 256)(line_width 3))
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(drawing
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(rectangle (rect 16 16 160 160)(line_width 1))
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(rectangle (rect 16 16 224 288)(line_width 1))
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)
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)

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/greybox_tmp/cbx_args.txt‎

Lines changed: 37 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -1,66 +1,39 @@
1-
BANDWIDTH_TYPE=AUTO
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CLK0_DIVIDE_BY=1
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CLK0_DUTY_CYCLE=50
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CLK0_MULTIPLY_BY=10
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CLK0_PHASE_SHIFT=0
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CLK1_DIVIDE_BY=1
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CLK1_DUTY_CYCLE=50
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CLK1_MULTIPLY_BY=20
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CLK1_PHASE_SHIFT=0
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COMPENSATE_CLOCK=CLK0
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INCLK0_INPUT_FREQUENCY=100000
1+
ADDRESS_REG_B=CLOCK0
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CLOCK_ENABLE_INPUT_A=BYPASS
3+
CLOCK_ENABLE_INPUT_B=BYPASS
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CLOCK_ENABLE_OUTPUT_A=BYPASS
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CLOCK_ENABLE_OUTPUT_B=BYPASS
6+
INDATA_REG_B=CLOCK0
7+
INIT_FILE=../../bin/onchip_mem.hex
128
INTENDED_DEVICE_FAMILY="Cyclone IV E"
13-
LPM_TYPE=altpll
14-
OPERATION_MODE=NORMAL
15-
PLL_TYPE=AUTO
16-
PORT_ACTIVECLOCK=PORT_UNUSED
17-
PORT_ARESET=PORT_USED
18-
PORT_CLKBAD0=PORT_UNUSED
19-
PORT_CLKBAD1=PORT_UNUSED
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PORT_CLKLOSS=PORT_UNUSED
21-
PORT_CLKSWITCH=PORT_UNUSED
22-
PORT_CONFIGUPDATE=PORT_UNUSED
23-
PORT_FBIN=PORT_UNUSED
24-
PORT_INCLK0=PORT_USED
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PORT_INCLK1=PORT_UNUSED
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PORT_LOCKED=PORT_USED
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PORT_PFDENA=PORT_UNUSED
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PORT_PHASECOUNTERSELECT=PORT_UNUSED
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PORT_PHASEDONE=PORT_UNUSED
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PORT_PHASESTEP=PORT_UNUSED
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PORT_PHASEUPDOWN=PORT_UNUSED
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PORT_PLLENA=PORT_UNUSED
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PORT_SCANACLR=PORT_UNUSED
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PORT_SCANCLK=PORT_UNUSED
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PORT_SCANCLKENA=PORT_UNUSED
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PORT_SCANDATA=PORT_UNUSED
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PORT_SCANDATAOUT=PORT_UNUSED
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PORT_SCANDONE=PORT_UNUSED
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PORT_SCANREAD=PORT_UNUSED
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PORT_SCANWRITE=PORT_UNUSED
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PORT_clk0=PORT_USED
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PORT_clk1=PORT_USED
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PORT_clk2=PORT_UNUSED
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PORT_clk3=PORT_UNUSED
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PORT_clk4=PORT_UNUSED
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PORT_clk5=PORT_UNUSED
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PORT_clkena0=PORT_UNUSED
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PORT_clkena1=PORT_UNUSED
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PORT_clkena2=PORT_UNUSED
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PORT_clkena3=PORT_UNUSED
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PORT_clkena4=PORT_UNUSED
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PORT_clkena5=PORT_UNUSED
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PORT_extclk0=PORT_UNUSED
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PORT_extclk1=PORT_UNUSED
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PORT_extclk2=PORT_UNUSED
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PORT_extclk3=PORT_UNUSED
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SELF_RESET_ON_LOSS_LOCK=OFF
58-
WIDTH_CLOCK=5
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LPM_TYPE=altsyncram
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NUMWORDS_A=2048
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NUMWORDS_B=2048
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OPERATION_MODE=BIDIR_DUAL_PORT
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OUTDATA_ACLR_A=NONE
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OUTDATA_ACLR_B=NONE
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OUTDATA_REG_A=UNREGISTERED
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OUTDATA_REG_B=UNREGISTERED
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POWER_UP_UNINITIALIZED=FALSE
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READ_DURING_WRITE_MODE_MIXED_PORTS=DONT_CARE
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READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_WITH_NBE_READ
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READ_DURING_WRITE_MODE_PORT_B=NEW_DATA_WITH_NBE_READ
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WIDTHAD_A=11
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WIDTHAD_B=11
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WIDTH_A=64
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WIDTH_B=64
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WIDTH_BYTEENA_A=1
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WIDTH_BYTEENA_B=1
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WRCONTROL_WRADDRESS_REG_B=CLOCK0
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DEVICE_FAMILY="Cyclone IV E"
60-
CBX_AUTO_BLACKBOX=ALL
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areset
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inclk
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inclk
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clk
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clk
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locked
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address_a
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address_b
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clock0
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data_a
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data_b
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rden_a
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rden_b
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wren_a
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wren_b
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q_a
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q_b

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/greybox_tmp/greybox_tmp/mgeua2.v‎

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//altsyncram ADDRESS_REG_B="CLOCK0" CBX_SINGLE_OUTPUT_FILE="ON" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" INDATA_REG_B="CLOCK0" INTENDED_DEVICE_FAMILY=""Cyclone IV E"" LPM_TYPE="altsyncram" NUMWORDS_A=131072 NUMWORDS_B=2048 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" READ_DURING_WRITE_MODE_PORT_A="NEW_DATA_NO_NBE_READ" READ_DURING_WRITE_MODE_PORT_B="NEW_DATA_NO_NBE_READ" WIDTH_A=1 WIDTH_B=64 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCSTATUS=3 WIDTHAD_A=17 WIDTHAD_B=11 WRCONTROL_WRADDRESS_REG_B="CLOCK0" address_a address_b clock0 data_a data_b q_a q_b wren_a wren_b
2+
//VERSION_BEGIN 17.0 cbx_mgl 2017:04:25:18:09:28:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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6+
7+
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// Copyright (C) 2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
12+
// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel MegaCore Function License Agreement, or other
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// applicable license agreement, including, without limitation,
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// that your use is for the sole purpose of programming logic
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// devices manufactured by Intel and sold by Intel or its
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// authorized distributors. Please refer to the applicable
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// agreement for further details.
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23+
24+
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//synthesis_resources = altsyncram 1
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
29+
module mgeua2
30+
(
31+
address_a,
32+
address_b,
33+
clock0,
34+
data_a,
35+
data_b,
36+
q_a,
37+
q_b,
38+
wren_a,
39+
wren_b) /* synthesis synthesis_clearbox=1 */;
40+
input [16:0] address_a;
41+
input [10:0] address_b;
42+
input clock0;
43+
input [0:0] data_a;
44+
input [63:0] data_b;
45+
output [0:0] q_a;
46+
output [63:0] q_b;
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input wren_a;
48+
input wren_b;
49+
50+
wire [0:0] wire_mgl_prim1_q_a;
51+
wire [63:0] wire_mgl_prim1_q_b;
52+
53+
altsyncram mgl_prim1
54+
(
55+
.address_a(address_a),
56+
.address_b(address_b),
57+
.clock0(clock0),
58+
.data_a(data_a),
59+
.data_b(data_b),
60+
.q_a(wire_mgl_prim1_q_a),
61+
.q_b(wire_mgl_prim1_q_b),
62+
.wren_a(wren_a),
63+
.wren_b(wren_b));
64+
defparam
65+
mgl_prim1.address_reg_b = "CLOCK0",
66+
mgl_prim1.clock_enable_input_a = "BYPASS",
67+
mgl_prim1.clock_enable_input_b = "BYPASS",
68+
mgl_prim1.clock_enable_output_a = "BYPASS",
69+
mgl_prim1.clock_enable_output_b = "BYPASS",
70+
mgl_prim1.indata_reg_b = "CLOCK0",
71+
mgl_prim1.intended_device_family = ""Cyclone IV E"",
72+
mgl_prim1.lpm_type = "altsyncram",
73+
mgl_prim1.numwords_a = 131072,
74+
mgl_prim1.numwords_b = 2048,
75+
mgl_prim1.operation_mode = "BIDIR_DUAL_PORT",
76+
mgl_prim1.outdata_aclr_a = "NONE",
77+
mgl_prim1.outdata_aclr_b = "NONE",
78+
mgl_prim1.outdata_reg_a = "CLOCK0",
79+
mgl_prim1.outdata_reg_b = "CLOCK0",
80+
mgl_prim1.power_up_uninitialized = "FALSE",
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mgl_prim1.read_during_write_mode_mixed_ports = "DONT_CARE",
82+
mgl_prim1.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
83+
mgl_prim1.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
84+
mgl_prim1.width_a = 1,
85+
mgl_prim1.width_b = 64,
86+
mgl_prim1.width_byteena_a = 1,
87+
mgl_prim1.width_byteena_b = 1,
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mgl_prim1.width_eccstatus = 3,
89+
mgl_prim1.widthad_a = 17,
90+
mgl_prim1.widthad_b = 11,
91+
mgl_prim1.wrcontrol_wraddress_reg_b = "CLOCK0";
92+
assign
93+
q_a = wire_mgl_prim1_q_a,
94+
q_b = wire_mgl_prim1_q_b;
95+
endmodule //mgeua2
96+
//VALID FILE

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