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miguelangelo78miguelangelo78
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Temporarily changed dual port RAM into single port RAM
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12 files changed

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-620
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12 files changed

+523
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‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/.qsys_edit/filters.xml‎

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<?xml version="1.0" encoding="UTF-8"?>
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<filters version="17.0" />

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/.qsys_edit/preferences.xml‎

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<?xml version="1.0" encoding="UTF-8"?>
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<preferences>
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<debug showDebugMenu="0" />
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<systemtable filter="All Interfaces">
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<columns>
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<connections preferredWidth="31" />
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<irq preferredWidth="34" />
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</columns>
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</systemtable>
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<library expandedCategories="Library,Project" />
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<window width="1100" height="800" x="0" y="0" />
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</preferences>

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/greybox_tmp/cbx_args.txt‎

Lines changed: 2 additions & 23 deletions
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@@ -1,39 +1,18 @@
1-
ADDRESS_REG_B=CLOCK0
21
CLOCK_ENABLE_INPUT_A=BYPASS
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CLOCK_ENABLE_INPUT_B=BYPASS
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CLOCK_ENABLE_OUTPUT_A=BYPASS
5-
CLOCK_ENABLE_OUTPUT_B=BYPASS
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INDATA_REG_B=CLOCK0
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INIT_FILE=../../bin/onchip_mem.hex
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INTENDED_DEVICE_FAMILY="Cyclone IV E"
9-
LPM_TYPE=altsyncram
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NUMWORDS_A=2048
11-
NUMWORDS_B=2048
12-
OPERATION_MODE=BIDIR_DUAL_PORT
6+
OPERATION_MODE=SINGLE_PORT
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OUTDATA_ACLR_A=NONE
14-
OUTDATA_ACLR_B=NONE
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OUTDATA_REG_A=UNREGISTERED
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OUTDATA_REG_B=UNREGISTERED
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POWER_UP_UNINITIALIZED=FALSE
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READ_DURING_WRITE_MODE_MIXED_PORTS=DONT_CARE
19-
READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_WITH_NBE_READ
20-
READ_DURING_WRITE_MODE_PORT_B=NEW_DATA_WITH_NBE_READ
10+
READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
2111
WIDTHAD_A=11
22-
WIDTHAD_B=11
2312
WIDTH_A=64
24-
WIDTH_B=64
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WIDTH_BYTEENA_A=1
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WIDTH_BYTEENA_B=1
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WRCONTROL_WRADDRESS_REG_B=CLOCK0
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DEVICE_FAMILY="Cyclone IV E"
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address_a
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address_b
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clock0
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data_a
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data_b
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rden_a
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rden_b
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wren_a
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wren_b
3818
q_a
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q_b

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/greybox_tmp/greybox_tmp/mg1pn.v‎

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1+
//altmem_init CBX_SINGLE_OUTPUT_FILE="ON" INIT_TO_ZERO="YES" INTENDED_DEVICE_FAMILY=""Cyclone IV E"" LPM_TYPE="altmem_init" NUMWORDS=16 PORT_ROM_DATA_READY="PORT_UNUSED" ROM_READ_LATENCY=1 WIDTH=1 WIDTHAD=4 clock dataout init init_busy ram_address ram_wren
2+
//VERSION_BEGIN 17.0 cbx_mgl 2017:04:25:18:09:28:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
3+
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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6+
7+
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// Copyright (C) 2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
12+
// (including device programming or simulation files), and any
13+
// associated documentation or information are expressly subject
14+
// to the terms and conditions of the Intel Program License
15+
// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel MegaCore Function License Agreement, or other
17+
// applicable license agreement, including, without limitation,
18+
// that your use is for the sole purpose of programming logic
19+
// devices manufactured by Intel and sold by Intel or its
20+
// authorized distributors. Please refer to the applicable
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// agreement for further details.
22+
23+
24+
25+
//synthesis_resources = altmem_init 1
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//synopsys translate_off
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`timescale 1 ps / 1 ps
28+
//synopsys translate_on
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module mg1pn
30+
(
31+
clock,
32+
dataout,
33+
init,
34+
init_busy,
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ram_address,
36+
ram_wren) /* synthesis synthesis_clearbox=1 */;
37+
input clock;
38+
output [0:0] dataout;
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input init;
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output init_busy;
41+
output [3:0] ram_address;
42+
output ram_wren;
43+
44+
wire [0:0] wire_mgl_prim1_dataout;
45+
wire wire_mgl_prim1_init_busy;
46+
wire [3:0] wire_mgl_prim1_ram_address;
47+
wire wire_mgl_prim1_ram_wren;
48+
49+
altmem_init mgl_prim1
50+
(
51+
.clock(clock),
52+
.dataout(wire_mgl_prim1_dataout),
53+
.init(init),
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.init_busy(wire_mgl_prim1_init_busy),
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.ram_address(wire_mgl_prim1_ram_address),
56+
.ram_wren(wire_mgl_prim1_ram_wren));
57+
defparam
58+
mgl_prim1.init_to_zero = "YES",
59+
mgl_prim1.intended_device_family = ""Cyclone IV E"",
60+
mgl_prim1.lpm_type = "altmem_init",
61+
mgl_prim1.numwords = 16,
62+
mgl_prim1.port_rom_data_ready = "PORT_UNUSED",
63+
mgl_prim1.rom_read_latency = 1,
64+
mgl_prim1.width = 1,
65+
mgl_prim1.widthad = 4;
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assign
67+
dataout = wire_mgl_prim1_dataout,
68+
init_busy = wire_mgl_prim1_init_busy,
69+
ram_address = wire_mgl_prim1_ram_address,
70+
ram_wren = wire_mgl_prim1_ram_wren;
71+
endmodule //mg1pn
72+
//VALID FILE

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/greybox_tmp/greybox_tmp/mglvp.v‎

Lines changed: 72 additions & 0 deletions
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1+
//altmem_init CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" INIT_TO_ZERO="YES" INTENDED_DEVICE_FAMILY=""Cyclone IV E"" LPM_TYPE="altmem_init" NUMWORDS=16 PORT_ROM_DATA_READY="PORT_UNUSED" ROM_READ_LATENCY=1 WIDTH=1 WIDTHAD=4 clock dataout init init_busy ram_address ram_wren
2+
//VERSION_BEGIN 17.0 cbx_mgl 2017:04:25:18:09:28:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
3+
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
4+
// altera message_off 10463
5+
6+
7+
8+
// Copyright (C) 2017 Intel Corporation. All rights reserved.
9+
// Your use of Intel Corporation's design tools, logic functions
10+
// and other software and tools, and its AMPP partner logic
11+
// functions, and any output files from any of the foregoing
12+
// (including device programming or simulation files), and any
13+
// associated documentation or information are expressly subject
14+
// to the terms and conditions of the Intel Program License
15+
// Subscription Agreement, the Intel Quartus Prime License Agreement,
16+
// the Intel MegaCore Function License Agreement, or other
17+
// applicable license agreement, including, without limitation,
18+
// that your use is for the sole purpose of programming logic
19+
// devices manufactured by Intel and sold by Intel or its
20+
// authorized distributors. Please refer to the applicable
21+
// agreement for further details.
22+
23+
24+
25+
//synthesis_resources = altmem_init 1
26+
//synopsys translate_off
27+
`timescale 1 ps / 1 ps
28+
//synopsys translate_on
29+
module mglvp
30+
(
31+
clock,
32+
dataout,
33+
init,
34+
init_busy,
35+
ram_address,
36+
ram_wren) /* synthesis synthesis_clearbox=1 */;
37+
input clock;
38+
output [0:0] dataout;
39+
input init;
40+
output init_busy;
41+
output [3:0] ram_address;
42+
output ram_wren;
43+
44+
wire [0:0] wire_mgl_prim1_dataout;
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wire wire_mgl_prim1_init_busy;
46+
wire [3:0] wire_mgl_prim1_ram_address;
47+
wire wire_mgl_prim1_ram_wren;
48+
49+
altmem_init mgl_prim1
50+
(
51+
.clock(clock),
52+
.dataout(wire_mgl_prim1_dataout),
53+
.init(init),
54+
.init_busy(wire_mgl_prim1_init_busy),
55+
.ram_address(wire_mgl_prim1_ram_address),
56+
.ram_wren(wire_mgl_prim1_ram_wren));
57+
defparam
58+
mgl_prim1.init_to_zero = "YES",
59+
mgl_prim1.intended_device_family = ""Cyclone IV E"",
60+
mgl_prim1.lpm_type = "altmem_init",
61+
mgl_prim1.numwords = 16,
62+
mgl_prim1.port_rom_data_ready = "PORT_UNUSED",
63+
mgl_prim1.rom_read_latency = 1,
64+
mgl_prim1.width = 1,
65+
mgl_prim1.widthad = 4;
66+
assign
67+
dataout = wire_mgl_prim1_dataout,
68+
init_busy = wire_mgl_prim1_init_busy,
69+
ram_address = wire_mgl_prim1_ram_address,
70+
ram_wren = wire_mgl_prim1_ram_wren;
71+
endmodule //mglvp
72+
//VALID FILE

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