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miguelangelo78miguelangelo78
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Added extremely basic ALU and Microcode Unit with debugging features
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12 files changed

+666
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‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/greybox_tmp/greybox_tmp/mg9pl.v‎

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//lpm_ram_dq CBX_SINGLE_OUTPUT_FILE="ON" INTENDED_DEVICE_FAMILY=""Cyclone IV E"" LPM_ADDRESS_CONTROL="REGISTERED" LPM_INDATA="REGISTERED" LPM_OUTDATA="REGISTERED" LPM_WIDTH=8 LPM_WIDTHAD=8 USE_EAB="OFF" address data inclock outclock q we
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//VERSION_BEGIN 17.0 cbx_mgl 2017:04:25:18:09:28:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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// Copyright (C) 2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel MegaCore Function License Agreement, or other
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// applicable license agreement, including, without limitation,
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// that your use is for the sole purpose of programming logic
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// devices manufactured by Intel and sold by Intel or its
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// authorized distributors. Please refer to the applicable
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// agreement for further details.
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//synthesis_resources = lpm_ram_dq 1
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module mg9pl
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(
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address,
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data,
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inclock,
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outclock,
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q,
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we) /* synthesis synthesis_clearbox=1 */;
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input [7:0] address;
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input [7:0] data;
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input inclock;
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input outclock;
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output [7:0] q;
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input we;
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wire [7:0] wire_mgl_prim1_q;
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lpm_ram_dq mgl_prim1
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(
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.address(address),
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.data(data),
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.inclock(inclock),
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.outclock(outclock),
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.q(wire_mgl_prim1_q),
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.we(we));
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defparam
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mgl_prim1.intended_device_family = ""Cyclone IV E"",
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mgl_prim1.lpm_address_control = "REGISTERED",
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mgl_prim1.lpm_indata = "REGISTERED",
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mgl_prim1.lpm_outdata = "REGISTERED",
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mgl_prim1.lpm_width = 8,
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mgl_prim1.lpm_widthad = 8,
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mgl_prim1.use_eab = "OFF";
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assign
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q = wire_mgl_prim1_q;
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endmodule //mg9pl
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//VALID FILE

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/rtl/onchip_rom/onchip_mem_microcode_segment.qip‎

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set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
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set_global_assignment -name IP_TOOL_VERSION "17.0"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "onchip_mem_microcode_segment.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "onchip_mem_microcode_segment_inst.v"]

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/rtl/onchip_rom/onchip_mem_microcode_segment.v‎

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// megafunction wizard: %ROM: 1-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram
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// ============================================================
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// File Name: onchip_mem_microcode_segment.v
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// Megafunction Name(s):
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// altsyncram
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
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// ************************************************************
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//Copyright (C) 2017 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel MegaCore Function License Agreement, or other
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//applicable license agreement, including, without limitation,
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//that your use is for the sole purpose of programming logic
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//devices manufactured by Intel and sold by Intel or its
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//authorized distributors. Please refer to the applicable
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//agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module onchip_mem_microcode_segment (
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address,
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clock,
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q);
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input [7:0] address;
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input clock;
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output [7:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [7:0] sub_wire0;
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wire [7:0] q = sub_wire0[7:0];
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altsyncram altsyncram_component (
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.address_a (address),
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.clock0 (clock),
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.q_a (sub_wire0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.address_b (1'b1),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_a ({8{1'b1}}),
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.data_b (1'b1),
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.eccstatus (),
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.q_b (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_a (1'b0),
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.wren_b (1'b0));
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defparam
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altsyncram_component.address_aclr_a = "NONE",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_output_a = "BYPASS",
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`ifdef NO_PLI
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altsyncram_component.init_file = "../../bin/onchip_mem_microcode_segment.rif"
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`else
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altsyncram_component.init_file = "../../bin/onchip_mem_microcode_segment.hex"
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`endif
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,
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altsyncram_component.intended_device_family = "Cyclone IV E",
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altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=ROM2",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 256,
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altsyncram_component.operation_mode = "ROM",
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altsyncram_component.outdata_aclr_a = "NONE",
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altsyncram_component.outdata_reg_a = "UNREGISTERED",
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altsyncram_component.widthad_a = 8,
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altsyncram_component.width_a = 8,
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altsyncram_component.width_byteena_a = 1;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
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// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
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// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: Clken NUMERIC "0"
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// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
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// Retrieval info: PRIVATE: JTAG_ID STRING "ROM2"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING "../../bin/onchip_mem_microcode_segment.hex"
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// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
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// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
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// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
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// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
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// Retrieval info: PRIVATE: WidthData NUMERIC "8"
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// Retrieval info: PRIVATE: rden NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: INIT_FILE STRING "../../bin/onchip_mem_microcode_segment.hex"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=ROM2"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
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// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
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// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
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// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
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// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL onchip_mem_microcode_segment.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL onchip_mem_microcode_segment.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL onchip_mem_microcode_segment.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL onchip_mem_microcode_segment.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL onchip_mem_microcode_segment_inst.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL onchip_mem_microcode_segment_bb.v FALSE
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// Retrieval info: LIB_FILE: altera_mf

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/rtl/onchip_rom/onchip_rom_microcode.qip‎

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set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
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set_global_assignment -name IP_TOOL_VERSION "17.0"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "onchip_rom_microcode.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "onchip_rom_microcode_inst.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "onchip_rom_microcode_bb.v"]

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