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This repo contains implementation of digital circuits and some projects related to them in Verilog language at different abstraction levels..

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MIT license
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EswarAdithya011/Verilog-HDL

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448 Commits
1 Bit Comparator
1 Bit Comparator
 
 
16 Bit Ripple Carry Adder
16 Bit Ripple Carry Adder
 
 
2 Bit Comparator Using 1 Bit Comparator
2 Bit Comparator Using 1 Bit Comparator
 
 
2x2 Bit Binary Multiplier
2x2 Bit Binary Multiplier
 
 
2x4 Decoder
2x4 Decoder
 
 
3x8 Decoder Using 2x4 Decoder
3x8 Decoder Using 2x4 Decoder
 
 
4 Bit Comparator Using 2 Bit Comparator
4 Bit Comparator Using 2 Bit Comparator
 
 
4 Bit Ripple Carry Adder
4 Bit Ripple Carry Adder
 
 
4x16 Decoder Using 2x4 Decoder
4x16 Decoder Using 2x4 Decoder
 
 
AND Gate Behavioral
AND Gate Behavioral
 
 
AOI (And-Or-Inverter)
AOI (And-Or-Inverter)
 
 
Asynchronous or BCD or Decade Up Counter (4-bit,Mod-10)
Asynchronous or BCD or Decade Up Counter (4-bit,Mod-10)
 
 
Asynchronous or Ripple Down Counter (3-bit,-ve Edge)
Asynchronous or Ripple Down Counter (3-bit,-ve Edge)
 
 
Asynchronous or Ripple Up Counter (3-bit,+ve Edge)
Asynchronous or Ripple Up Counter (3-bit,+ve Edge)
 
 
Asynchronous or Ripple Up Counter (3-bit,-ve Edge)
Asynchronous or Ripple Up Counter (3-bit,-ve Edge)
 
 
Asynchronous or Ripple Up Counter (mod-12)
Asynchronous or Ripple Up Counter (mod-12)
 
 
BCD Adder Using Binary Adder (4-bit)
BCD Adder Using Binary Adder (4-bit)
 
 
BCD to 7 Segment Display Decoder (CA)
BCD to 7 Segment Display Decoder (CA)
 
 
BCD to 7 Segment Display Decoder (CC)
BCD to 7 Segment Display Decoder (CC)
 
 
BCD to Excess-3 Converter
BCD to Excess-3 Converter
 
 
Barrel Shifter (8-bit) Using Multiplexer (2x1)
Barrel Shifter (8-bit) Using Multiplexer (2x1)
 
 
Binary Adder by Subtractor (4-bit)
Binary Adder by Subtractor (4-bit)
 
 
Binary Decrementer (4-bit)
Binary Decrementer (4-bit)
 
 
Binary Incrementer (4-bit)
Binary Incrementer (4-bit)
 
 
Binary Multiplier (4x3 bit)
Binary Multiplier (4x3 bit)
 
 
Binary Subtractor (2's Complement) Using 4-bit RCA
Binary Subtractor (2's Complement) Using 4-bit RCA
 
 
Binary to BCD Converter Using Double Dabble Algorithm
Binary to BCD Converter Using Double Dabble Algorithm
 
 
Binary to Gray Code Conversion
Binary to Gray Code Conversion
 
 
Boolean Function Using Decoder (POS)
Boolean Function Using Decoder (POS)
 
 
Boolean Function Using Decoder (SOP)
Boolean Function Using Decoder (SOP)
 
 
Boolean Function Using Multiplexer 4x1 (SOP,3 Var)
Boolean Function Using Multiplexer 4x1 (SOP,3 Var)
 
 
Boolean Function Using Multiplexer 8x1 (POS,4 Var)
Boolean Function Using Multiplexer 8x1 (POS,4 Var)
 
 
Boolean Function Using Multiplexer 8x1 (SOP,3 Var)
Boolean Function Using Multiplexer 8x1 (SOP,3 Var)
 
 
Braun Multiplier (8-bit)
Braun Multiplier (8-bit)
 
 
CMOS Inverter
CMOS Inverter
 
 
CMOS NAND Gate
CMOS NAND Gate
 
 
CMOS NOR Gate
CMOS NOR Gate
 
 
Carry Look Ahead Adder (4-bit)
Carry Look Ahead Adder (4-bit)
 
 
Carry Save Adder (4-bit)
Carry Save Adder (4-bit)
 
 
Carry Select Adder (4-bit)
Carry Select Adder (4-bit)
 
 
Carry Skip or Bypass Adder (4-bit)
Carry Skip or Bypass Adder (4-bit)
 
 
Checking for Palindrome of a Number
Checking for Palindrome of a Number
 
 
Clock Divider Circuit (100MHz → 1Hz)
Clock Divider Circuit (100MHz → 1Hz)
 
 
Clocked D Flip Flop
Clocked D Flip Flop
 
 
Clocked JK Flip Flop
Clocked JK Flip Flop
 
 
Clocked SR Flip Flop (NegEdge)
Clocked SR Flip Flop (NegEdge)
 
 
Clocked SR Flip Flop (Posedge)
Clocked SR Flip Flop (Posedge)
 
 
Clocked T Flip Flop
Clocked T Flip Flop
 
 
Conversion of D FlipFlop to T FlipFlop
Conversion of D FlipFlop to T FlipFlop
 
 
Conversion of JK FlipFlop to T FlipFlop
Conversion of JK FlipFlop to T FlipFlop
 
 
Conversion of SR FlipFlop to D FlipFlop
Conversion of SR FlipFlop to D FlipFlop
 
 
Conversion of SR FlipFlop to JK FlipFlop
Conversion of SR FlipFlop to JK FlipFlop
 
 
Demultiplexer (1x2)
Demultiplexer (1x2)
 
 
Demultiplexer (1x4 Using 1x2)
Demultiplexer (1x4 Using 1x2)
 
 
Design of 8-bit Arthimetic and Logical Unit
Design of 8-bit Arthimetic and Logical Unit
 
 
Digital Clock Counter (12hr Format)
Digital Clock Counter (12hr Format)
 
 
Electronic Voting Machine (EVM)
Electronic Voting Machine (EVM)
 
 
Encoder 4x2
Encoder 4x2
 
 
Even Parity Generator and Detector
Even Parity Generator and Detector
 
 
Excess-3 to BCD Converter
Excess-3 to BCD Converter
 
 
Frequency Divider Circuit - Divide by 4
Frequency Divider Circuit - Divide by 4
 
 
Full Adder Using Decoder
Full Adder Using Decoder
 
 
Full Adder Using Half Adder
Full Adder Using Half Adder
 
 
Full Subtractor Using Half Subtractor
Full Subtractor Using Half Subtractor
 
 
Function Implementation Using PROM
Function Implementation Using PROM
 
 
Gated D Latch Using NAND Gates
Gated D Latch Using NAND Gates
 
 
Gated SR Latch Using NAND Gates
Gated SR Latch Using NAND Gates
 
 
Gray to Binary Code Conversion
Gray to Binary Code Conversion
 
 
Half Adder
Half Adder
 
 
Half Subtractor
Half Subtractor
 
 
Implementation of CMOS Boolean Function (3-var)
Implementation of CMOS Boolean Function (3-var)
 
 
Johnson or Twisted Ring Counter (4-bit)
Johnson or Twisted Ring Counter (4-bit)
 
 
Linear Feedback Shift Register (4-bit)
Linear Feedback Shift Register (4-bit)
 
 
Logic Gates
Logic Gates
 
 
Master Slave JK FlipFlop Using SR and JK FlipFlop
Master Slave JK FlipFlop Using SR and JK FlipFlop
 
 
Mod-5 Synchronous Sequence Counter (Counts 0 → 1 → 3 → 7 → 2) with Self-Correction
Mod-5 Synchronous Sequence Counter (Counts 0 → 1 → 3 → 7 → 2) with Self-Correction
 
 
Monostable Multivibrator
Monostable Multivibrator
 
 
Multiplexer (16x1 Using 8x1,2x1)
Multiplexer (16x1 Using 8x1,2x1)
 
 
Multiplexer (2x1)
Multiplexer (2x1)
 
 
Multiplexer (32x1 Using 8x1,4x1)
Multiplexer (32x1 Using 8x1,4x1)
 
 
Multiplexer (4x1)
Multiplexer (4x1)
 
 
Multiplexer (8x1 Using 4x1,2x1)
Multiplexer (8x1 Using 4x1,2x1)
 
 
Multiplexer Using Transmission Gate (mux2x1)
Multiplexer Using Transmission Gate (mux2x1)
 
 
Octal to Binary Encoder
Octal to Binary Encoder
 
 
Odd Parity Generator and Detector
Odd Parity Generator and Detector
 
 
One Hot FSM
One Hot FSM
 
 
Parallel In Parallel Out Register
Parallel In Parallel Out Register
 
 
Parallel In Serial Out Register
Parallel In Serial Out Register
 
 
Parametric Register Array or File (32-bit)
Parametric Register Array or File (32-bit)
 
 
Priority Encoder (4-bit)
Priority Encoder (4-bit)
 
 
Read Only Memory (16x16)
Read Only Memory (16x16)
 
 
Ring Counter (Mod-6)
Ring Counter (Mod-6)
 
 
Ripple Carry Adder (16-bit)
Ripple Carry Adder (16-bit)
 
 
SR Latch Using NAND Gates
SR Latch Using NAND Gates
 
 
SR Latch Using NOR Gates
SR Latch Using NOR Gates
 
 
Serial In Parallel Out Register
Serial In Parallel Out Register
 
 
Serial In Serial Out Shift Left Register
Serial In Serial Out Shift Left Register
 
 
Serial In Serial Out Shift Right Register
Serial In Serial Out Shift Right Register
 
 
Sine Wave Generator
Sine Wave Generator
 
 
Squarer Circuit
Squarer Circuit
 
 

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Verilog Coding

Each of the project contains implementation details of each design with RTL's and Test bench. You can refer to simulation, schematic diagrams(.png) and tcl consoles for your references.

Tool Used:

Xilinx Vivado v2024.1 (64-bit)

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This repo contains implementation of digital circuits and some projects related to them in Verilog language at different abstraction levels..

Topics

verilog-hdl digitalelectronics

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