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Verilog Generator

A Codex-ready agent skill for disciplined Verilog-2001 RTL and FPGA design workflows.

Verilog Generator turns an AI coding agent into a more reliable RTL and FPGA engineering assistant. It provides trigger metadata, workflow instructions, interface templates, deterministic runtime helpers, examples, and validation gates for moving from confirmed hardware intent to synthesizable Verilog, FPGA-oriented module design, and self-checking testbenches.

This repository is primarily an agent skill package. The Python CLI is included as the deterministic execution layer, but the main interface is the skill surface an agent can load and follow.

Why It Exists

RTL work needs precision before code. Verilog Generator makes the agent confirm module names, ports, clock/reset behavior, pipeline expectations, interface family, reference behavior, and verification cases before producing artifacts.

Use it when an agent needs to work on:

• Synthesizable Verilog-2001 RTL modules.
• Self-checking Verilog testbenches.
• Python reference contracts for semantic comparison.
• AXI-Stream, AXI4-Lite, AXI4, AHB, APB, native, or custom interface shapes.
• Static validation, simulator readiness, workflow traces, and generated artifact review.

Skill Architecture

Workflow

What's New In v0.2.6

• Adds explicit generation shells for regular, deep_review, and agentic_repair, plus generation-only batch execution through the public facade.
• Expands the existing-RTL and verify-repair surface while keeping diagnostics, patch planning, and closure artifacts as first-class outputs.
• Continues the remote-first validation path and .settings/* configuration contract while refining workflow, provider, and validation orchestration for the public skill surface.

Repository Map

Path	Purpose
SKILL.md	Agent-facing routing, workflow, constraints, and tool usage rules.
agents/openai.yaml	UI metadata for skill lists and invocation chips.
runtime/verilog_generator/	Deterministic scaffolding, prompt rendering, extraction, validation, traces, and workflow state.
integration/verilog_adapter.py	Stable host-facing facade for workflow, prompt, and validation calls.
assets/interface_templates/	Reusable AXI-Stream, AXI4-Lite, AXI4, AHB, and APB interface patterns.
assets/refined_verilog_templates/	Reusable refined RTL shell snippets and grouped-port patterns.
assets/use_case_templates/	Packaged JESD, SPI, and mixed-signal reference templates with RTL, Tcl, and constraint skeletons.
assets/examples/	Example specs, remote fixtures, existing-RTL inputs, and refined template inputs for validation and regression checks.
evals/	Repo-local skill-effectiveness cases for workflow and remote-validation regressions.
RELEASE_RECEIPT.json	Provenance record for the imported v0.2.6 release package.

Quick Start

Tell your AI assistant: install https://github.com/Eriemon/verilog-generator

Place this repository in a Codex skill search path to use it as an agent skill. For runtime development and local checks:

python -m runtime.verilog_generator --version
python -m runtime.verilog_generator scaffold --name rtl_adapter --out .\reports\verilog\spec.json
python -m runtime.verilog_generator prompt --spec .\reports\verilog\spec.json --out .\reports\verilog\prompt.md

Static validation without external HDL tools:

python -m runtime.verilog_generator validate --spec .\reports\verilog\spec.json --path .\reports\verilog\generated --no-external

External validation requires real HDL tools. This project does not claim Vivado/xsim, VCS, iverilog, or yosys acceptance unless those tools actually run.

The v0.2.6 update adds explicit generation shells, keeps extending the existing-RTL/verify-repair path, and refines the remote-first validation contract around .settings/*.

Integration API

from integration.verilog_adapter import (
    analyze_existing_verilog,
    compare_verilog_semantics,
    refine_existing_verilog,
    render_verilog_prompt,
    run_verilog_batch,
    run_verilog_workflow,
    validate_verilog_artifacts,
    verify_existing_verilog,
)

• analyze_existing_verilog(...): analyze existing RTL into stable JSON contracts and a durable design explanation.
• refine_existing_verilog(...): plan controlled refinement flows such as testbench scaffold, style refine, partition assist, merge assist, and optimize assist.
• compare_verilog_semantics(...): compare candidate and reference RTL for interface and checkpoint drift.
• run_verilog_batch(...): execute generation-only batches across isolated case run directories.
• run_verilog_workflow(...): run or resume the staged RTL workflow.
• render_verilog_prompt(...): render prompts when a host owns the model call.
• validate_verilog_artifacts(...): validate generated RTL before downstream use.
• verify_existing_verilog(...): run the existing-RTL verify-repair loop and emit diagnostics, patch plans, and closure artifacts.

Scope

Verilog Generator is intentionally narrow:

• It generates Verilog-2001 .v artifacts and self-checking Verilog testbenches.
• It does not generate HLS, C/C++ kernels, or alternate RTL dialects.
• It prefers explicit logic over Verilog function and task blocks for easier waveform debugging.
• Local secrets, proprietary hardware designs, generated caches, and private remote-server details should stay out of the repository.
• Project-local remote settings should live under .settings/, and this public repository intentionally avoids keeping repo-tracked smoke/ or test-only validation source directories.

Affiliation

Jiyuan Liu and He Li are with the School of Electronic Science and Engineering, Southeast University. They are affiliated with the Heterogeneous Intelligence and Quantum Computing Laboratory (HIQC), which works on heterogeneous intelligence, quantum computing, and related computing systems research.

Contact

For questions, collaboration, or academic use, contact: erie@seu.edu.cn.

Citation

This skill is maintained by authors from the Heterogeneous Intelligence and Quantum Computing Laboratory(HIQC), School of Electronic Science and Engineering, Southeast University.

If this skill helps your research, teaching, or engineering workflow, please cite it. The canonical citation metadata is maintained in CITATION.cff.

@software{liu_2026_verilog_generator,
  author       = {Jiyuan Liu and He Li},
  title        = {{Verilog Generator}: An Agent Skill for Verilog-2001 RTL Workflows},
  year         = {2026},
  version      = {0.2.6},
  date         = {2026-05-29},
  url          = {https://github.com/Eriemon/verilog-generator},
  license      = {Apache-2.0},
  note         = {Agent skill package for disciplined Verilog-2001 RTL workflows}
}

License

Apache License 2.0. See LICENSE.