Bus wires and wire design

[lian-hsc]

If a chip is saved and then edited again, some information is lost or is not loaded correctly.
On the one hand, each input or output is always displayed as simple, regardless of which bus was set beforehand.
On the other hand, the wire design is not displayed correctly. Which in itself doesn't matter for the functionality of the chip, but with more complicated larger chips it makes it difficult to change things. However, this error only occurs if two or more wire go out from a starting point.

Digital.Logic.Sim.2022-08-31.10-41-36.mp4

It would also be cool if you could change and see the value for bus wires. Otherwise you have to create a lot of inputs again at some point.

[VitoBarra]

OK, I already noticed this problem but your video gave me some idea so I played around with pins and discovered that the problem exists only with unnamed pins, with the named one everything seems to work fine. So I now know where to see to fix this bug

[crispeeweevile]

OK, I already noticed this problem but your video gave me some idea so I played around with pins and discovered that the problem exists only with unnamed pins, with the named one everything seems to work fine. So I now know where to see to fix this bug

unnamed pins appear to always lose their pin type with no regard to whether they're named or not; however, I have confirmed that the lines themselves only move if the pins are unnamed