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Releases: DigitalLogicSimCommunity/Digital-Logic-Sim--Unofficial
Releases · DigitalLogicSimCommunity/Digital-Logic-Sim--Unofficial
v0.38
Mirror of release from https://github.com/DigitalLogicSimCommunity/Digital-Logic-Sim-CE
Changes Patch 3 (v0.38.0)
- Merges New chip dependecy Load System
- Merges Enable Vertical Synchronization (VSync)
- Fixes chip import button does nothing on Linux build
- Fixes 12
- Fixes 14
- Fixes Universal Darwin build not working File Selector.
- And hopefully adds file selector support for ARM Macs. I don't have one for testing.
Changes Patch 2 (v0.37)
- 41a9408deb512ee73f77cdc98f501c393d83d14a:
- fixes issue 11
- fixes new un-triggered raycaster when updating unity
- make exit button exit edit/view saved chip mode
- provide linux build to fulfill issue 10
Changes Patch 1 (v0.36.1)
- 715407dabb683f47e91685f462bcb8fb94a05f6b fixes issue 9
v0.36
New features:
- New chip folder system (by SwissCorePy)
- HDD contents are now persistent (by SwissCorePy)
- You can now zoom and move along the workspace (by SwissCorePy)
- New zoom helper, a minimap of where you are. So you don't get loss while zooming (by SwissCorePy)
- You can now change the scale of the objects in the workplace, allowing to create bigger and more ambitious circuits (by SwissCorePy)
- Bug fixes (by SwissCorePy)
Changes:
- Removed the option hide custom chips from Settings. Now there's a dedicated folder named "Advanced"
- Build performance improvement
- Etc
Features:
- New 4, 8 & 16 bus wires (By t4accer)
- New Run/Stop simulation button (by AOx0)
- Persistent settings (By Tigralt)
- 8x8 display (By Tigralt)
- Edit created chips:
- Button to spawn groups of input/output signal (By sagitarious12)
- New Hard Disk Drive: Its memory is the same across all projects. (By Turnip1234)
- Added hide/show setting to hide built-in chips (except AND & NOT) (by AOx0)
- Some UI tweaks.
Notes:
- Import of chips:
- Does not work on Apple macOS Universal build.
- It may don't work on Silicon Macs, but I don't know since I don't have one for testing.
Huge thanks to SwissCorePy for his work and making possible v0.36 and huge thanks to everyone that has contributed!
There is still a lot of work to do on the current features and lots of options to explore. Any contributions are welcome!
v0.37
Mirror of release from https://github.com/AOx0/Digital-Logic-Sim-CE
Changes Patch 2 (v0.37)
- 41a9408deb512ee73f77cdc98f501c393d83d14a:
- fixes issue # 11
- fixes new un-triggered raycaster when updating unity
- make exit button exit edit/view saved chip mode
- provide linux build to fulfill issue # 10
Changes v0.36.1 (Patch 1)
- 715407dabb683f47e91685f462bcb8fb94a05f6b fixes issue # 9
New features:
- New chip folder system (by SwissCorePy)
- HDD contents are now persistent (by SwissCorePy)
- You can now zoom and move along the workspace (by SwissCorePy)
- New zoom helper, a minimap of where you are. So you don't get loss while zooming (by SwissCorePy)
- You can now change the scale of the objects in the workplace, allowing to create bigger and more ambitious circuits (by SwissCorePy)
- Bug fixes (by SwissCorePy)
Changes:
- Removed the option hide custom chips from Settings. Now there's a dedicated folder named "Advanced"
- Build performance improvement
- Etc
Features:
- New 4, 8 & 16 bus wires (By t4accer)
- New Run/Stop simulation button (by AOx0)
- Persistent settings (By Tigralt)
- 8x8 display (By Tigralt)
- Edit created chips:
- Button to spawn groups of input/output signal (By sagitarious12)
- New Hard Disk Drive: Its memory is the same across all projects. (By Turnip1234)
- Added hide/show setting to hide built-in chips (except AND & NOT) (by AOx0)
- Some UI tweaks.
Notes:
- Import of chips:
- Does not work on Apple macOS Universal build.
- It may don't work on Silicon Macs, but I don't know since I don't have one for testing.
Huge thanks to SwissCorePy for his work and making possible v0.36 and huge thanks to everyone that has contributed!
There is still a lot of work to do on the current features and lots of options to explore. Any contributions are welcome!
v0.36.1
Mirror of release from https://github.com/AOx0/Digital-Logic-Sim-CE
Changes v0.36.1 (Patch 1)
- 715407dabb683f47e91685f462bcb8fb94a05f6b fixes issue #9
New features:
- New chip folder system (by SwissCorePy)
- HDD contents are now persistent (by SwissCorePy)
- You can now zoom and move along the workspace (by SwissCorePy)
- New zoom helper, a minimap of where you are. So you don't get loss while zooming (by SwissCorePy)
- You can now change the scale of the objects in the workplace, allowing to create bigger and more ambitious circuits (by SwissCorePy)
- Bug fixes (by SwissCorePy)
Changes:
- Removed the option hide custom chips from Settings. Now there's a dedicated folder named "Advanced"
- Build performance improvement
- Etc
Features:
- New 4, 8 & 16 bus wires (By t4accer)
- New Run/Stop simulation button (by AOx0)
- Persistent settings (By Tigralt)
- 8x8 display (By Tigralt)
- Edit created chips:
- Button to spawn groups of input/output signal (By sagitarious12)
- New Hard Disk Drive: Its memory is the same across all projects. (By Turnip1234)
- Added hide/show setting to hide built-in chips (except AND & NOT) (by AOx0)
- Some UI tweaks.
Notes:
- Import of chips:
- Does not work on Apple macOS Universal build.
- It may don't work on Silicon Macs, but I don't know since I don't have one for testing.
Huge thanks to SwissCorePy for his work and making possible v0.36 and huge thanks to everyone that has contributed!
There is still a lot of work to do on the current features and lots of options to explore. Any contributions are welcome!
v0.36
Mirror of release from https://github.com/AOx0/Digital-Logic-Sim-CE
New features:
- New chip folder system (by SwissCorePy)
- HDD contents are now persistent (by SwissCorePy)
- You can now zoom and move along the workspace (by SwissCorePy)
- New zoom helper, a minimap of where you are. So you don't get loss while zooming (by SwissCorePy)
- You can now change the scale of the objects in the workplace, allowing to create bigger and more ambitious circuits (by SwissCorePy)
- Bug fixes (by SwissCorePy)
Changes:
- Removed the option hide custom chips from Settings. Now there's a dedicated folder named "Advanced"
- Build performance improvement
- Etc
Features:
- New 4, 8 & 16 bus wires (By t4accer)
- New Run/Stop simulation button (by AOx0)
- Persistent settings (By Tigralt)
- 8x8 display (By Tigralt)
- Edit created chips:
- Button to spawn groups of input/output signal (By sagitarious12)
- New Hard Disk Drive: Its memory is the same across all projects. (By Turnip1234)
- Added hide/show setting to hide built-in chips (except AND & NOT) (by AOx0)
- Some UI tweaks.
Notes:
- Import of chips:
- Does not work on Apple macOS Universal build.
- It may don't work on Silicon Macs, but I don't know since I don't have one for testing.
Huge thanks to SwissCorePy for his work and making possible v0.36 and huge thanks to everyone that has contributed!
There is still a lot of work to do on the current features and lots of options to explore. Any contributions are welcome at https://github.com/AOx0/Digital-Logic-Sim-CE!
v0.35 (Unofficial)
This is a quick merge of all pull requests and forks to the original repo. All credit to the author of the application and to the PRs who developed this new features.
New features:
- New 4, 8 & 16 bus wires (By t4accer)
- New Run/Stop simulation button (by AOx0)
- Persistent settings (By Tigralt)
- 8x8 display (By Tigralt)
- Edit created chips:
- Import and Export chips (By Tigralt)
- Button to spawn groups of input/output signal (By sagitarious12)
- New Hard Disk Drive: Its memory is the same across all projects. (By Turnip1234)
- Added hide/show setting to hide built-in chips (except AND & NOT) (by AOx0)
- Some UI tweaks.
Added in v0.35:
- Added hide/show setting to hide built-in chips (except AND & NOT) (by AOx0)
- A chip that contains an 8x8 display, you select a pixel with the address and another bit for whether it's on. It is currently only black and white, but more configurability for this chip will be added in the future. (By Turnip1234)
Notes:
- No Builds for Silicon Macs nor Universal Build for macOS are possible yet due to StandaloneFileBrowser compatibility.
- No Builds for Linux 'cause I'm lazy. If you need one DM me on Twitter @AlecsOsornio
v0.34 (Unofficial)
This is a quick merge of all pull requests and forks to the original repo. All credit to the author of the application and to the PRs who developed this new features.
New features:
- New 4, 8 & 16 bus wires (By t4accer)
- New Run/Stop simulation button (by AOx0)
- Persistent settings (By Tigralt)
- Edit created chips:
- Import and Export chips (By Tigralt)
- Button to spawn groups of input/output signal (By sagitarious12)
- New Hard Disk Drive: Its memory is the same across all projects. (By Turnip1234)
- Some UI tweaks.
Fixed:
- Bug editing chip saves from version 0.2x on newer versions.
Notes:
- No Builds for Silicon Macs nor Universal Build for macOS are possible yet due to StandaloneFileBrowser compatibility.
v0.33 (Unofficial)
This is a quick merge of all pull requests and forks to the original repo. All credit to the author of the application and to the PRs who developed this new features.
New features:
- New 4, 8 & 16 bus wires (By t4accer)
- New Run/Stop simulation button (by AOx0)
- Persistent settings (By Tigralt)
- Edit created chips:
- Import and Export chips (By Tigralt)
- Button to spawn groups of input/output signal (By sagitarious12)
- New Hard Disk Drive: Its memory is the same across all projects. (By Turnip1234)
- Some UI tweaks.
Fixed:
- Bug when editing chip names
- Upgraded dependency packages version
Notes:
- No Builds for Silicon Macs nor Universal Build for macOS are possible yet due to StandaloneFileBrowser compatibility.
v0.32 (Unofficial)
This is a quick merge of all pull requests and forks to the original repo. All credit to the author of the application and to the PRs who developed this new features.
New features:
- New 4, 8 & 16 bus wires (By t4accer)
- New Run/Stop simulation button (by AOx0)
- Persistent settings (By Tigralt)
- Edit created chips:
- Import and Export chips (By Tigralt)
- Button to spawn groups of input/output signal (By sagitarious12)
- New Hard Disk Drive: Its memory is the same across all projects. (By Turnip1234)
- Some UI tweaks.
Fixed:
- App crash when cancel button is pressed at the export process
- Now users can't modify any built-in chips
- Version format fix
Notes:
- No Builds for Silicon Macs nor Universal Build for macOS are possible due to StandaloneFileBrowser compatibility.
v0.31 (Unofficial)
This is a quick merge of all pull requests and forks to the original repo. All credit to the author of the application and to the PRs who developed this new features.
New features:
- New 4, 8 & 16 bus wires (By t4accer)
- New Run/Stop simulation button (by AOx0)
- Edit created chips:
- Import and Export chips (By Tigralt)
- Button to spawn groups of input/output signal (By sagitarious12)
- New Hard Disk Drive: Its memory is the same in all the project. (By Turnip1234)
- Some UI tweaks.
v0.30 (Unofficial)
This is a quick merge of all pull requests of the original project to it. All credit to the author of the application and to the PRs who developed this new features.
New features:
- New 4, 8 & 16 bus wires
- New Run/Stop simulation button
- Edit created chips: Rename & Delete
- Button to spawn gropus of input/output (Max: 16)
- New Hard Disk Drive: Its memory is the same in all the project.
- Some UI tweaks.