Skip to content

Pull Upstream to devshFixes 2 #6

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 90 commits into from
Apr 18, 2025
Merged
Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
90 commits
Select commit Hold shift + click to select a range
5304402
[SM6.9] Allow native vectors longer than 4
Nov 21, 2024
e010223
Produce errors for long vectors in invalid contexts
Dec 5, 2024
cd72abe
fix assert for tesselation patch template args
Feb 18, 2025
4d5c2a2
Merge remote-tracking branch 'refs/remotes/origin/main' into longvec_…
Mar 3, 2025
1f12a3f
Refactor builtin type detection with attributes
Mar 3, 2025
de6ac33
Respond to feedback
Feb 21, 2025
76dde0d
Reaname and consolidate longvecs tests
Mar 3, 2025
765ab1c
Refactor, clarify, and expand testing
Mar 3, 2025
fb6538e
clang-format
Mar 3, 2025
19633b2
Handle subclasses and templates of longvector structs
Feb 25, 2025
466bb14
chore: autopublish 2025-03-05T20:50:11Z
github-actions[bot] Mar 5, 2025
66bb772
Identify matrices and vectors by attributes
Mar 6, 2025
20c2609
Use constant vector limit value for cached types
Mar 4, 2025
1b3ad42
Use definitiondata bits to determine long vector presence
Mar 3, 2025
d3fec83
Test for incomplete types in a number of builtin template-like objects
Mar 6, 2025
f7f1e3d
[Metal] Add experimental Metal support (#6805)
llvm-beanz Mar 7, 2025
4d3a2f5
[NFC] Improve time tracing data (#7146)
llvm-beanz Mar 7, 2025
50d1af5
Respond to feedback
Mar 10, 2025
eedab25
clang-format
Mar 10, 2025
e9cf3d2
Respond to feedback from a different PR
Mar 10, 2025
cc0ddc2
Rename long vector check func again
Mar 10, 2025
66e7d23
Respond to feedback
Mar 10, 2025
0102b3c
Use select indices instead of strings as parameters to longvec error
Mar 10, 2025
88479cf
fix formatting induced build break
Mar 10, 2025
7c8005a
[SM6.9] Allow native vectors longer than 4 (#7143)
Mar 11, 2025
a2979e7
Resolve some default error warnings (#7191)
bob80905 Mar 11, 2025
3d69171
Shorten bool conversion, remove unneeded change (#7197)
bob80905 Mar 12, 2025
ec5324d
NFC: Update HLSL_INTRINSIC struct for Flags and MinShaderModel fields…
tex3d Mar 13, 2025
24dedfd
[OMM] Implement front end diagnostics for OMM, including on TraceRayI…
bob80905 Mar 14, 2025
ebc8c5c
[NFC][Doc] Update HLSL to SPIR-V document (#7204)
lumina37 Mar 17, 2025
909c552
Create new raw buffer load lowering function (#7144)
Mar 17, 2025
9ba9689
[SPIR-V] Set RValue for the result of bitfield extract emulation (#7200)
Mar 18, 2025
503ef3c
Switch from tj-actions/changed-files to step-security/changed-files (…
llvm-beanz Mar 18, 2025
3ddf29b
Disallow swizzling on long vectors (#7215)
alsepkow Mar 18, 2025
6475f98
Actually fix the changed-files workflow (#7226)
llvm-beanz Mar 18, 2025
454bbf4
Fix typo in SPIR-V.rst (#7224)
s-perron Mar 19, 2025
6701eed
[SPIRV] Handle a cast to void (#7227)
s-perron Mar 19, 2025
0958e06
[SPIRV] Don't assume entry points are at the start of the worklist. (…
s-perron Mar 19, 2025
b2bcf21
Revert "[SPIRV] Use copy-in/copy-out for non-declaration (#7127)" (#7…
s-perron Mar 19, 2025
a0932fa
Add /bigobj compile option to MSVC build (#7228)
bob80905 Mar 19, 2025
eb02343
NFC: Make hlsl::IntrinsicOp enum values stable (#7231)
tex3d Mar 20, 2025
9e8a698
Lower RayQuery constructor to allocateRayQuery2 (#7205)
bob80905 Mar 20, 2025
8b3fae2
Use Wide String variants explicitly for Windows API calls (#7235)
bob80905 Mar 20, 2025
60e6c76
Add constraint to test that requires spirv support (#7241)
bob80905 Mar 21, 2025
b646ad3
[SPIRV] Update submodules and fix test (#7243)
s-perron Mar 21, 2025
94596e1
[SPIRV] Allow sampled type to be half for universal (#7252)
s-perron Mar 24, 2025
9a06f4d
Consolidate buffer store translation (#7251)
Mar 24, 2025
c5f62d9
[SER] Patch 1: HitObject type lowering and SM 6.9 enablement (#7097)
simoll Mar 25, 2025
7269298
[SER] HitObject_MakeNop|Miss DXIL opcodes and verification tests (#7201)
simoll Mar 25, 2025
33bc44a
Update github actions versions to enable coverage (#7183)
Mar 25, 2025
1eb83c7
Allow native vectors for LLVM operations (#7155)
Mar 26, 2025
d8aad78
Add support for KHR_compute_shader_derivatives (#7249)
iagoCL Mar 26, 2025
31a2f58
[SPIR-V] Fix usage of indices in subfunctions (#7242)
Keenuts Mar 27, 2025
0fa207a
Update DXIL.rst (#7254)
alsepkow Mar 27, 2025
b7b532b
[SPIR-V] Update submodules (#7269)
cassiebeckley Mar 27, 2025
eb16959
Update print statements to be compatible with Python 3 (#7268)
raoanag Mar 27, 2025
5ff9cbc
[Sema] Add and test new Subobject Attribute (#7258)
bob80905 Mar 27, 2025
206b775
[OMM] Add D3D Flag RAYTRACING_PIPELINE_FLAG_ALLOW_OPACITY_MICROMAPS, …
bob80905 Mar 28, 2025
3035d31
Require CMake 3.17, remove CMP0051 (#7287)
llvm-beanz Apr 1, 2025
30bfd82
NFC: Infrastructure changes for DXIL op vector and multi-dim overload…
tex3d Apr 1, 2025
a13938d
PIX: Check for existing PIX UAV in roots sigs before adding it again …
jeffnn Apr 1, 2025
2f357a9
Fix assert due to unreachable discard (#7289)
amaiorano Apr 2, 2025
572aef5
Disable code owners in main (#7298)
llvm-beanz Apr 2, 2025
9eb7119
[SPIRV] Implements vk::BufferPointer proposal (#7163)
danbrown-amd Apr 2, 2025
2b1c2e6
Fix typo in exec tests comment (#7299)
alsepkow Apr 2, 2025
3b1a29b
[OMM] Add DXR Entry point test, non-library target test, conforming t…
bob80905 Apr 2, 2025
6556410
[SPIR-V] Implement QuadAny and QuadAll (#7266)
cassiebeckley Apr 3, 2025
9010244
Add UUID compiler extension check on Clang (#7286)
urshanselmann Apr 3, 2025
6a73640
Update DXC's CONTRIBUTING file (#7265)
llvm-beanz Apr 3, 2025
c9170e5
Update SPIRV-Tools (#7303)
s-perron Apr 3, 2025
85f3432
Fixes non-SPIR-V build, broken by PR #7163 ([SPIRV] Implements vk::Bu…
danbrown-amd Apr 3, 2025
e50f599
[NFC] Standardize DxilValidation variable capitalization (#7307)
Apr 4, 2025
0ffd60a
[SM6.9] Native vector load/store lowering (#7292)
Apr 4, 2025
9e91844
[NFC] containsLongVector -> ContainsLongVector (#7255)
llvm-beanz Apr 7, 2025
dc4a2b6
[PIX] Add a pass for PIX to log missing NonUniformResourceIndex usage…
nopandbrk Apr 7, 2025
c940161
Bump cryptography from 43.0.1 to 44.0.1 in /utils/git (#7220)
dependabot[bot] Apr 8, 2025
5d2fa92
[SM6.9] Enable trivial native vector Dxil Operations plus a few (#7324)
llvm-beanz Apr 9, 2025
90bfb66
[SER] 'reordercoherent' HLSL attribute and DXIL encoding (#7250)
simoll Apr 10, 2025
bc9044a
[SER] REORDER_SCOPE Barrier semantic flag (#7263)
simoll Apr 10, 2025
0168df1
[SER] HitObject_FromRayQuery[WithAttrs] DXIL opcodes and check-pass t…
simoll Apr 12, 2025
94f9275
[SER] HitObject accessors DXIL opcodes and check-pass tests (#7276)
simoll Apr 13, 2025
8280d0f
[SER] HitObject_Invoke|TraceRay DXIL opcodes and check-pass test (#7278)
simoll Apr 14, 2025
b5a9cd5
[SER] MaybeReorderThread DXIL opcode and validation (#7256)
simoll Apr 14, 2025
47e11af
[spirv] Handles rvalue as implicit object argument of vk::BufferPoint…
danbrown-amd Apr 14, 2025
30a7579
[spirv] Fixes vk::BufferPointer constructor expression construction. …
danbrown-amd Apr 15, 2025
ea3d846
[SER] Declare all SER HLSL intrinsics (#7347)
simoll Apr 15, 2025
5f18e2b
Add HctGen of DXIL.rst back to build without LLVM_BUILD_DOCS required…
tex3d Apr 15, 2025
10bff13
Fix field names in long vector DICompositeType (#7332)
simoll Apr 16, 2025
0a470b5
[SPIRV] Remove patch decoration from gl_TessCoord (#7187) (#7349)
SteveUrquhart Apr 16, 2025
0beaa76
[SER] MaybeReorderThread + Make(Nop|Miss) HLSL -> DXIL lowering and t…
simoll Apr 17, 2025
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Prev Previous commit
Next Next commit
[SER] REORDER_SCOPE Barrier semantic flag (microsoft#7263)
- HLSL REORDER_SCOPE flag (available from SM6.9)
- Make validator accept REORDER_SCOPE from DXIL 1.9
  • Loading branch information
simoll authored Apr 10, 2025
commit bc9044adc7356896eeb1f37a3846f4fef8ed241e
4 changes: 3 additions & 1 deletion include/dxc/DXIL/DxilConstants.h
Original file line number Diff line number Diff line change
Expand Up @@ -1905,7 +1905,9 @@ enum class BarrierSemanticFlag : uint32_t {
GroupSync = 0x00000001, // GROUP_SYNC
GroupScope = 0x00000002, // GROUP_SCOPE
DeviceScope = 0x00000004, // DEVICE_SCOPE
ValidMask = 0x00000007,
LegacyFlags = 0x00000007,
ReorderScope = 0x00000008, // REORDER_SCOPE
ValidMask = 0x0000000F,
GroupFlags = GroupSync | GroupScope,
};

Expand Down
1 change: 1 addition & 0 deletions include/dxc/DXIL/DxilOperations.h
Original file line number Diff line number Diff line change
Expand Up @@ -151,6 +151,7 @@ class OP {
static bool IsDxilOpBarrier(OpCode C);
static bool BarrierRequiresGroup(const llvm::CallInst *CI);
static bool BarrierRequiresNode(const llvm::CallInst *CI);
static bool BarrierRequiresReorder(const llvm::CallInst *CI);
static DXIL::BarrierMode TranslateToBarrierMode(const llvm::CallInst *CI);
static void GetMinShaderModelAndMask(OpCode C, bool bWithTranslation,
unsigned &major, unsigned &minor,
Expand Down
40 changes: 39 additions & 1 deletion lib/DXIL/DxilOperations.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@
///////////////////////////////////////////////////////////////////////////////

#include "dxc/DXIL/DxilOperations.h"
#include "dxc/DXIL/DxilConstants.h"
#include "dxc/DXIL/DxilInstructions.h"
#include "dxc/DXIL/DxilModule.h"
#include "dxc/Support/Global.h"
Expand Down Expand Up @@ -3024,6 +3025,30 @@ bool OP::BarrierRequiresNode(const llvm::CallInst *CI) {
}
}

bool OP::BarrierRequiresReorder(const llvm::CallInst *CI) {
OpCode Opcode = OP::GetDxilOpFuncCallInst(CI);
switch (Opcode) {
case OpCode::BarrierByMemoryType: {
DxilInst_BarrierByMemoryType Barrier(const_cast<CallInst *>(CI));
if (!isa<ConstantInt>(Barrier.get_SemanticFlags()))
return false;
unsigned SemanticFlags = Barrier.get_SemanticFlags_val();
return (SemanticFlags & static_cast<unsigned>(
DXIL::BarrierSemanticFlag::ReorderScope)) != 0U;
}
case OpCode::BarrierByMemoryHandle: {
DxilInst_BarrierByMemoryHandle Barrier(const_cast<CallInst *>(CI));
if (!isa<ConstantInt>(Barrier.get_SemanticFlags()))
return false;
unsigned SemanticFlags = Barrier.get_SemanticFlags_val();
return (SemanticFlags & static_cast<unsigned>(
DXIL::BarrierSemanticFlag::ReorderScope)) != 0U;
}
default:
return false;
}
}

DXIL::BarrierMode OP::TranslateToBarrierMode(const llvm::CallInst *CI) {
OpCode opcode = OP::GetDxilOpFuncCallInst(CI);
switch (opcode) {
Expand All @@ -3046,6 +3071,12 @@ DXIL::BarrierMode OP::TranslateToBarrierMode(const llvm::CallInst *CI) {
semanticFlags = barrier.get_SemanticFlags_val();
}

// Disallow SM6.9+ semantic flags.
if (semanticFlags &
~static_cast<unsigned>(DXIL::BarrierSemanticFlag::LegacyFlags)) {
return DXIL::BarrierMode::Invalid;
}

// Mask to legacy flags, if allowed.
memoryTypeFlags = MaskMemoryTypeFlagsIfAllowed(
memoryTypeFlags, (unsigned)DXIL::MemoryTypeFlag::LegacyFlags);
Expand Down Expand Up @@ -3467,10 +3498,17 @@ void OP::GetMinShaderModelAndMask(const llvm::CallInst *CI,
minor = 8;
}
}
if (BarrierRequiresReorder(CI)) {
major = 6;
minor = 9;
mask &= SFLAG(Library) | SFLAG(RayGeneration);
return;
}
if (BarrierRequiresNode(CI)) {
mask &= SFLAG(Library) | SFLAG(Node);
return;
} else if (BarrierRequiresGroup(CI)) {
}
if (BarrierRequiresGroup(CI)) {
mask &= SFLAG(Library) | SFLAG(Compute) | SFLAG(Amplification) |
SFLAG(Mesh) | SFLAG(Node);
return;
Expand Down
16 changes: 12 additions & 4 deletions lib/DxilValidation/DxilValidation.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1628,6 +1628,15 @@ std::string GetLaunchTypeStr(DXIL::NodeLaunchType LT) {
}
}

static unsigned getSemanticFlagValidMask(const ShaderModel *pSM) {
unsigned DxilMajor, DxilMinor;
pSM->GetDxilVersion(DxilMajor, DxilMinor);
// DXIL version >= 1.9
if (hlsl::DXIL::CompareVersions(DxilMajor, DxilMinor, 1, 9) < 0)
return static_cast<unsigned>(hlsl::DXIL::BarrierSemanticFlag::LegacyFlags);
return static_cast<unsigned>(hlsl::DXIL::BarrierSemanticFlag::ValidMask);
}

static void ValidateDxilOperationCallInProfile(CallInst *CI,
DXIL::OpCode Opcode,
const ShaderModel *pSM,
Expand Down Expand Up @@ -1838,8 +1847,8 @@ static void ValidateDxilOperationCallInProfile(CallInst *CI,
(unsigned)hlsl::DXIL::MemoryTypeFlag::ValidMask,
"memory type", "BarrierByMemoryType");
ValidateBarrierFlagArg(ValCtx, CI, DI.get_SemanticFlags(),
(unsigned)hlsl::DXIL::BarrierSemanticFlag::ValidMask,
"semantic", "BarrierByMemoryType");
getSemanticFlagValidMask(pSM), "semantic",
"BarrierByMemoryType");
if (!IsLibFunc && ShaderKind != DXIL::ShaderKind::Node &&
OP::BarrierRequiresNode(CI)) {
ValCtx.EmitInstrError(CI, ValidationRule::InstrBarrierRequiresNode);
Expand All @@ -1855,8 +1864,7 @@ static void ValidateDxilOperationCallInProfile(CallInst *CI,
: "barrierByMemoryHandle";
DxilInst_BarrierByMemoryHandle DIMH(CI);
ValidateBarrierFlagArg(ValCtx, CI, DIMH.get_SemanticFlags(),
(unsigned)hlsl::DXIL::BarrierSemanticFlag::ValidMask,
"semantic", OpName);
getSemanticFlagValidMask(pSM), "semantic", OpName);
if (!IsLibFunc && ShaderKind != DXIL::ShaderKind::Node &&
OP::BarrierRequiresNode(CI)) {
ValCtx.EmitInstrError(CI, ValidationRule::InstrBarrierRequiresNode);
Expand Down
2 changes: 1 addition & 1 deletion tools/clang/include/clang/Basic/DiagnosticSemaKinds.td
Original file line number Diff line number Diff line change
Expand Up @@ -7986,7 +7986,7 @@ def err_hlsl_barrier_invalid_memory_flags: Error<
"UAV_MEMORY, GROUP_SHARED_MEMORY, NODE_INPUT_MEMORY, NODE_OUTPUT_MEMORY flags">;
def err_hlsl_barrier_invalid_semantic_flags: Error<
"invalid SemanticFlags for Barrier operation; expected 0 or some combination of "
"GROUP_SYNC, GROUP_SCOPE, DEVICE_SCOPE flags">;
"GROUP_SYNC, GROUP_SCOPE, DEVICE_SCOPE%select{|, REORDER_SCOPE}0 flags">;
def warn_hlsl_barrier_group_memory_requires_group: Warning<
"GROUP_SHARED_MEMORY specified for Barrier operation when context has no visible group">,
InGroup<HLSLBarrier>, DefaultError;
Expand Down
6 changes: 5 additions & 1 deletion tools/clang/lib/AST/ASTContextHLSL.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -718,6 +718,8 @@ void hlsl::AddSamplerFeedbackConstants(ASTContext &context) {

/// <summary> Adds all enums for Barrier intrinsic</summary>
void hlsl::AddBarrierConstants(ASTContext &context) {
VersionTuple VT69 = VersionTuple(6, 9);

AddTypedefPseudoEnum(
context, "MEMORY_TYPE_FLAG",
{{"UAV_MEMORY", (unsigned)DXIL::MemoryTypeFlag::UavMemory},
Expand All @@ -730,7 +732,9 @@ void hlsl::AddBarrierConstants(ASTContext &context) {
context, "BARRIER_SEMANTIC_FLAG",
{{"GROUP_SYNC", (unsigned)DXIL::BarrierSemanticFlag::GroupSync},
{"GROUP_SCOPE", (unsigned)DXIL::BarrierSemanticFlag::GroupScope},
{"DEVICE_SCOPE", (unsigned)DXIL::BarrierSemanticFlag::DeviceScope}});
{"DEVICE_SCOPE", (unsigned)DXIL::BarrierSemanticFlag::DeviceScope},
{"REORDER_SCOPE", (unsigned)DXIL::BarrierSemanticFlag::ReorderScope,
ConstructAvailabilityAttribute(context, VT69)}});
}

static Expr *IntConstantAsBoolExpr(clang::Sema &sema, uint64_t value) {
Expand Down
22 changes: 16 additions & 6 deletions tools/clang/lib/Sema/SemaHLSL.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -11576,7 +11576,8 @@ static bool CheckFinishedCrossGroupSharingCall(Sema &S, CXXMethodDecl *MD,
return false;
}

static bool CheckBarrierCall(Sema &S, FunctionDecl *FD, CallExpr *CE) {
static bool CheckBarrierCall(Sema &S, FunctionDecl *FD, CallExpr *CE,
const hlsl::ShaderModel *SM) {
DXASSERT(FD->getNumParams() == 2, "otherwise, unknown Barrier overload");

// Emit error when MemoryTypeFlags are known to be invalid.
Expand Down Expand Up @@ -11606,12 +11607,18 @@ static bool CheckBarrierCall(Sema &S, FunctionDecl *FD, CallExpr *CE) {
llvm::APSInt SemanticFlagsVal;
if (SemanticFlagsExpr->isIntegerConstantExpr(SemanticFlagsVal, S.Context)) {
SemanticFlags = SemanticFlagsVal.getLimitedValue();
if ((uint32_t)SemanticFlags &
~(uint32_t)DXIL::BarrierSemanticFlag::ValidMask) {
uint32_t ValidMask = 0U;
if (SM->IsSM69Plus()) {
ValidMask =
static_cast<unsigned>(hlsl::DXIL::BarrierSemanticFlag::ValidMask);
} else {
ValidMask =
static_cast<unsigned>(hlsl::DXIL::BarrierSemanticFlag::LegacyFlags);
}
if ((uint32_t)SemanticFlags & ~ValidMask) {
S.Diags.Report(SemanticFlagsExpr->getExprLoc(),
diag::err_hlsl_barrier_invalid_semantic_flags)
<< (uint32_t)SemanticFlags
<< (uint32_t)DXIL::BarrierSemanticFlag::ValidMask;
<< SM->IsSM69Plus();
return true;
}
}
Expand Down Expand Up @@ -11654,14 +11661,17 @@ void Sema::CheckHLSLFunctionCall(FunctionDecl *FDecl, CallExpr *TheCall,
if (!IsBuiltinTable(IntrinsicAttr->getGroup()))
return;

const auto *SM =
hlsl::ShaderModel::GetByName(getLangOpts().HLSLProfile.c_str());

hlsl::IntrinsicOp opCode = (hlsl::IntrinsicOp)IntrinsicAttr->getOpcode();
switch (opCode) {
case hlsl::IntrinsicOp::MOP_FinishedCrossGroupSharing:
CheckFinishedCrossGroupSharingCall(*this, cast<CXXMethodDecl>(FDecl),
TheCall->getLocStart());
break;
case hlsl::IntrinsicOp::IOP_Barrier:
CheckBarrierCall(*this, FDecl, TheCall);
CheckBarrierCall(*this, FDecl, TheCall, SM);
break;
#ifdef ENABLE_SPIRV_CODEGEN
case hlsl::IntrinsicOp::IOP_Vkreinterpret_pointer_cast:
Expand Down
Original file line number Diff line number Diff line change
@@ -0,0 +1,53 @@
// RUN: %dxilver 1.9 | %dxc -T lib_6_9 %s | %D3DReflect %s | %FileCheck %s -check-prefixes=RDAT

// Check that stage flags are set correctly still for different barrier modes in SM 6.9.

// RDAT: FunctionTable[{{.*}}] = {

RWByteAddressBuffer BAB : register(u1, space0);

// RDAT-LABEL: UnmangledName: "fn_barrier_reorder"
// RDAT: FeatureInfo1: 0
// RDAT: FeatureInfo2: 0
// RDAT: ShaderStageFlag: (Library | RayGeneration)
// RDAT: MinShaderTarget: 0x60069

[noinline] export
void fn_barrier_reorder() {
Barrier(UAV_MEMORY, REORDER_SCOPE);
}

// RDAT-LABEL: UnmangledName: "fn_barrier_reorder2"
// RDAT: FeatureInfo1: 0
// RDAT: FeatureInfo2: 0
// RDAT: ShaderStageFlag: (Library | RayGeneration)
// RDAT: MinShaderTarget: 0x60069

[noinline] export
void fn_barrier_reorder2() {
Barrier(BAB, REORDER_SCOPE);
}

// RDAT-LABEL: UnmangledName: "rg_barrier_reorder_in_call"
// RDAT: FeatureInfo1: 0
// RDAT: FeatureInfo2: 0
// RDAT: ShaderStageFlag: (RayGeneration)
// RDAT: MinShaderTarget: 0x70069

[shader("raygeneration")]
void rg_barrier_reorder_in_call() {
fn_barrier_reorder();
BAB.Store(0, 0);
}

// RDAT-LABEL: UnmangledName: "rg_barrier_reorder_in_call2"
// RDAT: FeatureInfo1: 0
// RDAT: FeatureInfo2: 0
// RDAT: ShaderStageFlag: (RayGeneration)
// RDAT: MinShaderTarget: 0x70069

[shader("raygeneration")]
void rg_barrier_reorder_in_call2() {
fn_barrier_reorder2();
BAB.Store(0, 0);
}
Original file line number Diff line number Diff line change
@@ -0,0 +1,68 @@
; RUN: %dxilver 1.9 | %dxv %s

; Buffer Definitions:
;
;
; Resource Bindings:
;
; Name Type Format Dim ID HLSL Bind Count
; ------------------------------ ---------- ------- ----------- ------- -------------- ------
; BAB UAV byte r/w U0 u1 1
;
target datalayout = "e-m:e-p:32:32-i1:32-i8:32-i16:32-i32:32-i64:64-f16:32-f32:32-f64:64-n8:16:32:64"
target triple = "dxil-ms-dx"

%dx.types.Handle = type { i8* }
%dx.types.ResourceProperties = type { i32, i32 }
%struct.RWByteAddressBuffer = type { i32 }

@"\01?BAB@@3URWByteAddressBuffer@@A" = external constant %dx.types.Handle, align 4

; Function Attrs: nounwind
define void @"\01?main@@YAXXZ"() #0 {
%1 = load %dx.types.Handle, %dx.types.Handle* @"\01?BAB@@3URWByteAddressBuffer@@A", align 4
call void @dx.op.barrierByMemoryType(i32 244, i32 1, i32 8) ; BarrierByMemoryType(MemoryTypeFlags,SemanticFlags)
%2 = call %dx.types.Handle @dx.op.createHandleForLib.dx.types.Handle(i32 160, %dx.types.Handle %1) ; CreateHandleForLib(Resource)
%3 = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle %2, %dx.types.ResourceProperties { i32 4107, i32 0 }) ; AnnotateHandle(res,props) resource: RWByteAddressBuffer
call void @dx.op.barrierByMemoryHandle(i32 245, %dx.types.Handle %3, i32 8) ; BarrierByMemoryHandle(object,SemanticFlags)
ret void
}

; Function Attrs: noduplicate nounwind
declare void @dx.op.barrierByMemoryType(i32, i32, i32) #1

; Function Attrs: noduplicate nounwind
declare void @dx.op.barrierByMemoryHandle(i32, %dx.types.Handle, i32) #1

; Function Attrs: nounwind readnone
declare %dx.types.Handle @dx.op.annotateHandle(i32, %dx.types.Handle, %dx.types.ResourceProperties) #2

; Function Attrs: nounwind readonly
declare %dx.types.Handle @dx.op.createHandleForLib.dx.types.Handle(i32, %dx.types.Handle) #3

attributes #0 = { nounwind }
attributes #1 = { noduplicate nounwind }
attributes #2 = { nounwind readnone }
attributes #3 = { nounwind readonly }

!dx.version = !{!0}
!dx.valver = !{!0}
!dx.shaderModel = !{!1}
!dx.resources = !{!2}
!dx.typeAnnotations = !{!5}
!dx.entryPoints = !{!9, !11}

!0 = !{i32 1, i32 9}
!1 = !{!"lib", i32 6, i32 9}
!2 = !{null, !3, null, null}
!3 = !{!4}
!4 = !{i32 0, %struct.RWByteAddressBuffer* bitcast (%dx.types.Handle* @"\01?BAB@@3URWByteAddressBuffer@@A" to %struct.RWByteAddressBuffer*), !"BAB", i32 0, i32 1, i32 1, i32 11, i1 false, i1 false, i1 false, null}
!5 = !{i32 1, void ()* @"\01?main@@YAXXZ", !6}
!6 = !{!7}
!7 = !{i32 1, !8, !8}
!8 = !{}
!9 = !{null, !"", null, !2, !10}
!10 = !{i32 0, i64 8589934608}
!11 = !{void ()* @"\01?main@@YAXXZ", !"\01?main@@YAXXZ", null, null, !12}
!12 = !{i32 8, i32 7, i32 5, !13}
!13 = !{i32 0}
Original file line number Diff line number Diff line change
@@ -0,0 +1,8 @@
// RUN: %dxc -Tlib_6_8 -verify %s

[Shader("compute")]
[numthreads(1, 1, 1)]
void main() {
// expected-error@+1{{invalid SemanticFlags for Barrier operation; expected 0 or some combination of GROUP_SYNC, GROUP_SCOPE, DEVICE_SCOPE flags}}
Barrier(0, REORDER_SCOPE);
}
Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
// RUN: %dxc -T lib_6_9 -E main %s | FileCheck %s

RWByteAddressBuffer BAB : register(u1, space0);

[shader("raygeneration")]
void main() {
// CHECK: call void @dx.op.barrierByMemoryType(i32 244, i32 1, i32 8)
Barrier(UAV_MEMORY, REORDER_SCOPE);

// CHECK: call void @dx.op.barrierByMemoryHandle(i32 245, %dx.types.Handle %{{[^ ]+}}, i32 8)
Barrier(BAB, REORDER_SCOPE);
}
Loading