I build deterministic real-time FPGA sensing systems and physics-driven simulation engines from first principles.

Physical theory → mathematical models → algorithms → RTL/C/C++ → instrumentation → analysis & visualization

Overview • Current Focus • Skills & Tools • Featured Work • Featured Report • Results • Ecosystem • GitHub Activity • Repositories • Contact

I design and implement deeply structured engineering systems, including:

• Hardware-only FPGA sensing + control pipelines (no soft CPU)
• CDC-disciplined real-time visualization via VGA HUD overlays
• Barnes–Hut gravitational simulation engines (2D & 3D)
• Telemetry chains: FPGA → UART → CSV → MATLAB/Python analysis
• Documentation-first workflows (RTL + math + LaTeX reports)

My work emphasizes correctness, timing determinism, structured dataflow, and rigorous modeling.

• Expanding FPGA_Signal_Control_System into full occupancy-map sensor fusion
• Porting spatial simulation primitives toward hardware acceleration
• Building instrumentation-first FPGA visualization workflows

• FPGA/RTL Design — synchronous systems, CDC safety, fixed-point arithmetic
• Embedded Systems — peripheral bring-up, register-level engineering
• Physics Simulation — N-body gravity, numerical stability, multipole methods
• Data Pipelines — telemetry decoding, structured datasets, modeling workflows

• CDC-safe Verilog modules (UART, I²C, PWM, VGA, XADC front-ends)
• Ready/valid datapaths, deterministic FSM pipelines
• Q1.15 fixed-point mapping between physical units and digital logic
• Vivado non-project automation with Tcl + timing closure discipline

• Barnes–Hut engines using quadtrees + Morton-encoded hashed octrees
• O(N log N) multipole approximations with symplectic integration
• Energy tracking, parameter sweeps, visualization tooling

A hardware-only physics control laboratory with live deterministic visualization.

• Time-of-Flight distance mapping + surveying modes
• VGA HUD overlay at 640×480 @ 60 Hz
• UART telemetry streaming at 2 Mb/s with CRC framing
• Temperature → PWM fan control via fixed-point pipelines
• Strict SYS→PIX CDC snapshot buses for tear-free rendering

High-performance gravitational modeling built around:

• Adaptive quadtrees + Morton-ordered hashed octrees
• O(N log N) scaling multipole approximations
• Leapfrog / velocity Verlet symplectic integration
• Real-time visualization and stability diagnostics

A central part of my work is producing full engineering-grade documentation that unifies:

physical modeling → mathematical formalization → RTL architecture → verification → visualization.

A thesis-style systems document covering deterministic FPGA sensing pipelines.

• CDC doctrine and why asynchronous sampling is explicitly rejected
• Fixed-point physical unit mapping (Q formats, scaling invariants)
• SYS→PIX snapshot bus architecture for tear-free VGA HUD rendering
• Sensor fusion telemetry pipelines (ToF + Sonar + temperature + motion)
• Instrumentation-first verification: logic analyzer + scope correlation

🔗 PDF Report:
Sonar_Fusion_Signal_CAT_Thesis (3).pdf

🔗 LaTeX Source: (add repo/docs link when uploaded)

Click to expand project visuals

FPGA Vivado Implementation

Top-Level RTL Schematic

Hardware Bench Setup

MATLAB Telemetry + Modeling View

VGA Real-Time HUD Output

A summary of the languages, tools, and engineering environments that support my work — spanning
RTL hardware systems, physics-driven simulation, and instrumentation-first verification.

Verilog RTL (hardware-only pipelines, no soft CPU):

• VGA pixel-domain HUD compositing and deterministic overlays
• UART telemetry framing + CRC validation at multi-megabit rates
• I²C sensor polling FSMs and peripheral sequencing
• PWM generation for fan + mixed-signal control outputs
• XADC front-ends for temperature + analog monitoring
• Strict SYS→PIX CDC snapshot buses for tear-free visualization
• Ready/valid streaming datapaths and hierarchical module partitioning

Toolchain + implementation discipline:

• Vivado timing closure, constraint design (XDC), and CDC correctness
• Non-project scripted builds using Tcl regeneration flows
• Hardware-first verification: scope + logic analyzer correlation

My FPGA work is developed and verified on real bench hardware, with an emphasis on
signal integrity, timing determinism, and instrumentation-grounded debugging.

• Digilent Nexys A7-100T (Artix-7)
  Primary RTL prototyping platform for synchronous sensor fusion, VGA visualization, and telemetry pipelines.

• ISL29501 Time-of-Flight (ToF) Ranging Module
  Used for distance mapping, survey sweeps, and real-time occupancy instrumentation.

• ADXL362 Ultra-Low-Power Accelerometer (SPI)
  Provides tilt/orientation telemetry and motion-aware HUD visualization.

• VGA Pixel Pipeline (PIX domain)
  Dedicated ~25 MHz rendering domain for deterministic HUD overlays.

• System Control Pipeline (SYS domain)
  Dedicated ~100 MHz synchronous domain for sensor acquisition, control FSMs, and telemetry generation.

• CDC Snapshot Boundary (SYS → PIX)
  Explicit multi-bit coherence doctrine: tear-free visualization through registered snapshot buses.

• Digilent Analog Discovery 3
  Mixed-signal verification of real-time control outputs, PWM behavior, and protocol timing.

• Digilent Analog Discovery 2
  Logic analyzer + oscilloscope correlation for UART framing, I²C transactions, and synchronous pipeline validation.

Hardware verification is treated as part of the design contract:
simulation proves logic, instrumentation proves physics.

C++17 high-performance engines:

• Barnes–Hut gravitational simulation (2D + 3D)
• Adaptive quadtrees + Morton-encoded hashed octrees
• O(N log N) multipole approximation pipelines
• Symplectic integration (leapfrog, velocity Verlet)
• Energy stability diagnostics and parameter exploration

Mathematical emphasis:

• Physical invariants carried through discretization
• Error analysis, stability constraints, fixed-point mapping philosophy

C + structured systems programming:

• UART log decoding and binary packet parsing
• Dataset modeling tools and automated CSV transformation pipelines
• Robust debugging utilities and file-structure introspection

MATLAB / Python scientific tooling:

• Telemetry ingestion: FPGA → UART → CSV → analysis
• Real-time plotting, range-map visualization, diagnostic sweeps
• Post-processing pipelines for sensor fusion evaluation

• Register-level microcontroller workflows (HCS12 / ARM coursework)
• Bare-metal peripheral reasoning: timers, ADCs, GPIO conditioning
• Hardware/software boundary discipline: signals treated as physics, not abstractions

LaTeX + technical writing:

• Full thesis-style project reports with derivations and system invariants
• CDC doctrine chapters: explicitly defining allowed vs forbidden crossings
• Architecture diagrams, timing tables, and verification methodology

Markdown + repository engineering:

• Documentation-first repo structure (code + theory + instrumentation)
• READMEs written as engineering references, not marketing blurbs

Automation + build repeatability:

• Tcl-based Vivado rebuild scripts
• Structured directory layouts supporting regeneration and scaling

Engineering is treated as a closed loop:
physical model → mathematical formalism → digital implementation → instrumentation → verification → visualization

Real-time FPGA sensing/control system with ToF mapping, VGA HUD, telemetry, fan/PIR/encoder integration.

2D gravitational engine with adaptive quadtree refinement and interactive visualization.

3D Barnes–Hut simulation using Morton-encoded hashed octrees for scalable spatial subdivision.

C pipeline for dataset modeling, transformations, diagnostics, and telemetry-grade tooling.

• LinkedIn: https://www.linkedin.com/in/david-richardson-0099281b6/
• Email: 02richardsondavid@gmail.com
• Resume PDF: Resumë (9).pdf
• Portfolio: https://davidrichardson02.github.io/

Structured. Physics-driven. Deterministic engineering from first principles.