Fix race condition in signal_and_wait #1740
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Signed-off-by: Caleb Metz <caleb.metz@datadoghq.com>
Signed-off-by: Caleb Metz <caleb.metz@datadoghq.com>
Signed-off-by: Caleb Metz <caleb.metz@datadoghq.com>
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What does this PR do?
Fixes a rare race condition in signal_and_wait that loom does not catch (without adding an explicit yield point)
Motivation
Fix race condition.
Additional Notes
The first commit adds the loom tests to prove that 1. we have a race condition, and 2. loom is unable to explore the right interleaving without an explicit yield point
The second commit applied the fix
If you checkout the first commit expect the loom test
signal_and_wait_race_proof_with_yeildto failHere is my writeup. It has a lot more context and details
https://datadoghq.atlassian.net/wiki/x/dwBHcAE