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Update scalafmt-core to 3.10.1 #306

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1f984dc
Update scalafmt-core to 3.10.1
scala-steward Oct 19, 2025
d03662b
Reformat with scalafmt 3.10.1
scala-steward Oct 19, 2025
4377847
Add 'Reformat with scalafmt 3.10.1' to .git-blame-ignore-revs
scala-steward Oct 19, 2025
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2 changes: 2 additions & 0 deletions .git-blame-ignore-revs
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@@ -0,0 +1,2 @@
# Scala Steward: Reformat with scalafmt 3.10.1
d03662b095bfb6591c96449275382bc596814f71
2 changes: 1 addition & 1 deletion .scalafmt.conf
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@@ -1,4 +1,4 @@
version = 3.9.10
version = 3.10.1
runner.dialect = scala3

maxColumn = 100
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2 changes: 1 addition & 1 deletion compiler/ir/src/main/scala/dfhdl/compiler/analysis/DFConditionalAnalysis.scala
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Expand Up @@ -75,7 +75,7 @@ extension [CB <: DFConditional.Block](cb: CB)(using MemberGetSet)
.toSet
selectorVal.dfType match
case _ if complexPattern => None
case DFBits(Int(width)) =>
case DFBits(Int(width)) =>
if (constSet.exists(_.isBubble)) None // currently not checking don't-care patterns
else Some((1 << width) == constSet.size)
case dec: DFDecimal =>
Expand Down
2 changes: 1 addition & 1 deletion compiler/ir/src/main/scala/dfhdl/compiler/ir/HasRefCompare.scala
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Expand Up @@ -5,7 +5,7 @@ trait HasRefCompare[T <: HasRefCompare[T]]:
final def =~(that: T)(using MemberGetSet): Boolean =
cachedCompare match
case Some(prevCompare, result) if prevCompare eq that => result
case _ =>
case _ =>
val res = this `prot_=~` that
cachedCompare = Some(that, res)
res
Expand Down
2 changes: 1 addition & 1 deletion compiler/stages/src/main/scala/dfhdl/compiler/stages/DropUnreferenced.scala
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Expand Up @@ -22,7 +22,7 @@ case object DropUnreferencedAnons extends Stage, NoCheckStage:
// skipping over conditional headers that can be considered values as well.
case _: DFConditional.Header => None
// idents are always kept
case Ident(_) => None
case Ident(_) => None
case m: DFVal if m.isAnonymous && m.originMembers.isEmpty =>
Some(m -> Patch.Remove())
case _ => None
Expand Down
6 changes: 3 additions & 3 deletions compiler/stages/src/main/scala/dfhdl/compiler/stages/MatchToIf.scala
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Expand Up @@ -80,7 +80,7 @@ case object MatchToIf extends Stage:
list match
case cond :: Nil => Some(cond)
case Nil => None
case _ =>
case _ =>
Some(dfhdl.core.DFVal.Func(dfhdl.core.DFBool, reductionOp, list))
pattern match
case Pattern.Singleton(DFRef(const: DFVal.Const)) =>
Expand Down Expand Up @@ -118,8 +118,8 @@ case object MatchToIf extends Stage:
val patternCondOpt = getPatternCondOpt(selector, c.pattern)
val guardRef: DFConditional.Block.GuardRef =
(c.getGuardOption, patternCondOpt) match
case (_, None) => c.guardRef
case (None, Some(cond)) => cond.asIR.refTW[DFIfElseBlock]
case (_, None) => c.guardRef
case (None, Some(cond)) => cond.asIR.refTW[DFIfElseBlock]
case (Some(guardVal), Some(cond)) =>
val combinedGuard = guardVal.asValOf[dfhdl.core.DFBool] && cond
combinedGuard.asIR.refTW[DFIfElseBlock]
Expand Down
18 changes: 9 additions & 9 deletions compiler/stages/src/main/scala/dfhdl/compiler/stages/SanityCheck.scala
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Expand Up @@ -28,7 +28,7 @@ case class SanityCheck(skipAnonRefCheck: Boolean) extends Stage:
else memberSet += m
// check for missing references
m.getRefs.foreach {
case _: DFRef.Empty => // do nothing
case _: DFRef.Empty => // do nothing
case r if !refTable.contains(r) =>
reportViolation(s"Missing ref $r for the member: $m")
case _ => // do nothing
Expand Down Expand Up @@ -72,7 +72,7 @@ case class SanityCheck(skipAnonRefCheck: Boolean) extends Stage:
// check that anonymous values are referenced exactly once
m match
case dfVal: DFVal if dfVal.isAllowedMultipleReferences => // skip named
case dfVal: DFVal =>
case dfVal: DFVal =>
val deps = dfVal.getReadDeps
if (deps.size > 1)
reportViolation(
Expand All @@ -85,7 +85,7 @@ case class SanityCheck(skipAnonRefCheck: Boolean) extends Stage:
dfVal match
case ch: DFConditional.Header if ch.dfType == DFUnit =>
case Ident(_) =>
case _ =>
case _ =>
reportViolation(
s"""|An anonymous value has no references.
|Referenced value: $dfVal""".stripMargin
Expand All @@ -108,7 +108,7 @@ case class SanityCheck(skipAnonRefCheck: Boolean) extends Stage:
memberSet.foreach { m =>
m.getRefs.foreach {
case _: DFRef.Empty => // skip empty referenced
case r =>
case r =>
originRefTableMutable.get(r).foreach { prevMember =>
def originViolation(addedText: String) = reportViolation(
s"""|Ref $r has more than one origin member$addedText.
Expand All @@ -121,7 +121,7 @@ case class SanityCheck(skipAnonRefCheck: Boolean) extends Stage:
r.get match
// global references can be shared across types
case dfVal: DFVal.CanBeGlobal if dfVal.isGlobal => // no violation
case _ =>
case _ =>
if (!(prevMember isSameOwnerDesignAs m))
originViolation(" from a different design")
case _ => originViolation("")
Expand All @@ -133,13 +133,13 @@ case class SanityCheck(skipAnonRefCheck: Boolean) extends Stage:
// or the referencing member is a design parameter
originRefTableMutable.foreach {
case (_: DFRef.TypeRef, _) => // do nothing
case (r, originMember) =>
case (r, originMember) =>
r.get match
case targetVal: DFVal if targetVal.isAnonymous && targetVal.isGlobal =>
originMember match
case originVal: DFVal if originVal.isGlobal =>
case _: DFVal.DesignParam =>
case _ =>
case _ =>
reportViolation(
s"""|A global anonymous member is referenced by a non-global member.
|Target member: ${targetVal}
Expand Down Expand Up @@ -189,7 +189,7 @@ case class SanityCheck(skipAnonRefCheck: Boolean) extends Stage:
m match // still in current owner
case o: DFOwner => ownershipCheck(o, nextMembers) // entering new owner
case _ => ownershipCheck(currentOwner, nextMembers) // new non-member found
case Nil => // Done! All is OK
case Nil => // Done! All is OK
case m :: _ => // not in current owner
if (currentOwner.isTop)
println(
Expand All @@ -212,7 +212,7 @@ case class SanityCheck(skipAnonRefCheck: Boolean) extends Stage:
getSet.designDB.members.foreach {
// goto statement can reference later steps
case _: Goto =>
case m =>
case m =>
m.getRefs.foreach {
case r @ DFRef(rm) if !discoveredMembers.contains(rm) =>
m match
Expand Down
32 changes: 16 additions & 16 deletions compiler/stages/src/test/scala/StagesSpec/ExplicitClkRstCfgSpec.scala
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Expand Up @@ -44,7 +44,7 @@ class ExplicitClkRstCfgSpec extends StageSpec(stageCreatesUnrefAnons = true):
RstCfg(inclusionPolicy = RstCfg.InclusionPolicy.AlwaysAtTop)
val eo = summon[options.ElaborationOptions]
// force DFC with these elaboration options modifications (this is required because no @top annotation)
val dfc = DFC.empty(eo)
val dfc = DFC.empty(eo)
def gen(using DFC): dfhdl.core.Design =
class ID extends RTDesign:
val x = SInt(16) <> IN
Expand Down Expand Up @@ -117,8 +117,8 @@ class ExplicitClkRstCfgSpec extends StageSpec(stageCreatesUnrefAnons = true):
y := x

class IDTop extends EDDesign:
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val dmn1 = new RTDomain:
val id = ID()
id.x <> x
Expand Down Expand Up @@ -163,8 +163,8 @@ class ExplicitClkRstCfgSpec extends StageSpec(stageCreatesUnrefAnons = true):
y := x

class IDTop extends EDDesign:
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val dmn1 = new RTDomain:
val id = ID()
id.x <> x
Expand Down Expand Up @@ -209,8 +209,8 @@ class ExplicitClkRstCfgSpec extends StageSpec(stageCreatesUnrefAnons = true):
y := x

class IDTop extends RTDesign:
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val dmn1 = new RTDomain:
val id = ID()
id.x <> x
Expand Down Expand Up @@ -255,8 +255,8 @@ class ExplicitClkRstCfgSpec extends StageSpec(stageCreatesUnrefAnons = true):
y := x

class IDTop extends RTDesign:
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val dmn1 = new RTDomain:
val id = ID()
id.x <> x
Expand Down Expand Up @@ -305,8 +305,8 @@ class ExplicitClkRstCfgSpec extends StageSpec(stageCreatesUnrefAnons = true):
y := x.reg(1, init = 5)

class IDTop extends RTDesign:
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val dmn1 = new RTDomain(cfg):
val id = ID()
id.x <> x
Expand Down Expand Up @@ -435,8 +435,8 @@ class ExplicitClkRstCfgSpec extends StageSpec(stageCreatesUnrefAnons = true):
y := x

class IDTop extends EDDesign:
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val dmn1 = new RTDomain:
val id = ID()
id.x <> x
Expand Down Expand Up @@ -489,9 +489,9 @@ class ExplicitClkRstCfgSpec extends StageSpec(stageCreatesUnrefAnons = true):
gen.clk <> src.clk
gen.rst <> src.rst
class ID extends RTDesign(cfg):
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val clkGen = new ClkGen(cfg, genCfg)
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val clkGen = new ClkGen(cfg, genCfg)
val internal = new RTDomain(genCfg):
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
Expand Down
8 changes: 4 additions & 4 deletions compiler/stages/src/test/scala/StagesSpec/ExplicitNamedVarsSpec.scala
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Expand Up @@ -30,8 +30,8 @@ class ExplicitNamedVarsSpec extends StageSpec:
}
test("Named conditional expression") {
class ID extends DFDesign:
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val z: SInt[16] <> VAL =
if (x > 0) 5
else if (x < 0) x + 1
Expand Down Expand Up @@ -63,8 +63,8 @@ class ExplicitNamedVarsSpec extends StageSpec:
}
test("Nested named conditional expression") {
class ID extends DFDesign:
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val x = SInt(16) <> IN
val y = SInt(16) <> OUT
val z: SInt[16] <> VAL =
if (x > 0)
if (x > 5) 5
Expand Down
30 changes: 15 additions & 15 deletions compiler/stages/src/test/scala/StagesSpec/VHDLProcToVerilogSpec.scala
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Expand Up @@ -7,11 +7,11 @@ import dfhdl.compiler.stages.vhdlProcToVerilog
class VHDLProcToVerilogSpec extends StageSpec:
test("Only clock") {
class ID extends EDDesign:
val clk = Bit <> IN
val x1 = SInt(16) <> IN
val y1 = SInt(16) <> OUT
val x2 = SInt(16) <> IN
val y2 = SInt(16) <> OUT
val clk = Bit <> IN
val x1 = SInt(16) <> IN
val y1 = SInt(16) <> OUT
val x2 = SInt(16) <> IN
val y2 = SInt(16) <> OUT
val proc1 = process(clk):
if (clk.rising)
y1 := x1
Expand All @@ -37,16 +37,16 @@ class VHDLProcToVerilogSpec extends StageSpec:
}
test("if reset else clock") {
class ID extends EDDesign:
val clk = Bit <> IN
val rst = Bit <> IN
val x1 = SInt(16) <> IN
val y1 = SInt(16) <> OUT
val x2 = SInt(16) <> IN
val y2 = SInt(16) <> OUT
val x3 = SInt(16) <> IN
val y3 = SInt(16) <> OUT
val x4 = SInt(16) <> IN
val y4 = SInt(16) <> OUT
val clk = Bit <> IN
val rst = Bit <> IN
val x1 = SInt(16) <> IN
val y1 = SInt(16) <> OUT
val x2 = SInt(16) <> IN
val y2 = SInt(16) <> OUT
val x3 = SInt(16) <> IN
val y3 = SInt(16) <> OUT
val x4 = SInt(16) <> IN
val y4 = SInt(16) <> OUT
val proc1 = process(clk, rst):
if (rst == 0)
y1 := 0
Expand Down
2 changes: 1 addition & 1 deletion compiler/stages/src/test/scala/StagesSpec/ViaConnectionSpec.scala
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Expand Up @@ -112,7 +112,7 @@ class ViaConnectionSpec extends StageSpec(stageCreatesUnrefAnons = true):
val id1_y = SInt(16) <> VAR
val id2_x = SInt(16) <> VAR
val id2_y = SInt(16) <> VAR
val id1 = new ID():
val id1 = new ID():
this.x <> id1_x
this.y <> id1_y
val id2 = new ID():
Expand Down
2 changes: 1 addition & 1 deletion core/src/main/scala/dfhdl/core/DFMember.scala
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Expand Up @@ -11,7 +11,7 @@ type DFMemberAny = DFMember[ir.DFMember]
object DFMember:
extension [T <: ir.DFMember](member: DFMember[T])
inline def asIR: T = (member.irValue: @unchecked) match
case memberIR: T @unchecked => memberIR
case memberIR: T @unchecked => memberIR
case err: DFError.REG_DIN[?] if err.firstTime =>
err.firstTime = false
throw err
Expand Down
2 changes: 1 addition & 1 deletion core/src/main/scala/dfhdl/core/DFWhile.scala
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Expand Up @@ -35,7 +35,7 @@ def COMB_LOOP(using
while (!stop)
ownerIR match
case cb: ir.DFConditional.Block => ownerIR = cb.getOwner
case lb: ir.DFLoop.Block =>
case lb: ir.DFLoop.Block =>
if (lineEnd == -1)
lineEnd = lb.meta.position.lineEnd
else if (lineEnd != lb.meta.position.lineEnd)
Expand Down
2 changes: 1 addition & 1 deletion core/src/main/scala/dfhdl/core/SameElementsVector.scala
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Expand Up @@ -43,7 +43,7 @@ object SameElementsVector:
named
)
width match
case width: Int => constVec[W](width, named)
case width: Int => constVec[W](width, named)
case width: DFConstInt32 @unchecked =>
val singleBit = constVec[1](1, named = false)
import DFBits.Val.Ops.repeat
Expand Down
28 changes: 14 additions & 14 deletions core/src/main/scala/dfhdl/core/ShowType.scala
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Expand Up @@ -19,18 +19,18 @@ extension [T](using quotes: Quotes)(tpe: quotes.reflect.TypeRepr)
case '[Tuple1[d]] => TypeRepr.of[d].showType
case _ => d.showType
tpe.asTypeOf[DFTypeAny] match
case '[DFBit] => "Bit"
case '[DFBool] => "Boolean"
case '[DFBits[w]] => s"Bits[${Type.show[w]}]"
case '[DFUInt[w]] => s"UInt[${Type.show[w]}]"
case '[DFInt32] => "Int"
case '[DFSInt[w]] => s"SInt[${Type.show[w]}]"
case '[DFEnum[t]] => Type.show[t]
case '[DFDouble] => "Double"
case '[DFTime] => "Time"
case '[DFFreq] => "Freq"
case '[DFNumber] => "Number"
case '[DFString] => "String"
case '[DFBit] => "Bit"
case '[DFBool] => "Boolean"
case '[DFBits[w]] => s"Bits[${Type.show[w]}]"
case '[DFUInt[w]] => s"UInt[${Type.show[w]}]"
case '[DFInt32] => "Int"
case '[DFSInt[w]] => s"SInt[${Type.show[w]}]"
case '[DFEnum[t]] => Type.show[t]
case '[DFDouble] => "Double"
case '[DFTime] => "Time"
case '[DFFreq] => "Freq"
case '[DFNumber] => "Number"
case '[DFString] => "String"
case '[DFVector[t, d]] =>
s"${TypeRepr.of[t].showDFType} X ${TypeRepr.of[d].showVecLength}"
case '[DFType[ir.DFVector, Args2[t, d]]] =>
Expand Down Expand Up @@ -65,11 +65,11 @@ extension [T](using quotes: Quotes)(tpe: quotes.reflect.TypeRepr)
tpe.asTypeOf[Any] match
case '[DFValAny] => tpe.showDFVal
case '[DFTypeAny] => tpe.showDFType
case '[Tuple] =>
case '[Tuple] =>
tpe.showTuple(_.showType).mkStringBrackets
case '[ContextFunction1[DFC, t]] => TypeRepr.of[t].showType
case '[dfhdl.internals.Inlined[t]] => Type.show[t]
case _ =>
case _ =>
tpe match
case _: TermRef => s"${tpe.show}.type"
case _ => tpe.show
Expand Down
3 changes: 2 additions & 1 deletion core/src/test/scala/CoreSpec/DFBitsSpec.scala
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Expand Up @@ -61,7 +61,8 @@ class DFBitsSpec extends DFSpec:
b"100",
1,
h"9"
).toBits; t10.assertPosition(0, 5, 17, 15)
).toBits;
t10.assertPosition(0, 5, 17, 15)
def twice(value: Bits[Int] <> VAL): Bits[Int] <> DFRET = (value, value)
val t11 = twice(t1); t11.assertPosition(0, 1, 17, 26)
assertLatestDesignDclPosition(2, 1, 7, 78)
Expand Down
2 changes: 1 addition & 1 deletion docs/getting-started/hello-world/scala-project/.scalafmt.conf
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@@ -1,4 +1,4 @@
version = 3.9.10
version = 3.10.1
runner.dialect = scala3

maxColumn = 100
Expand Down
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