Merge tag 'drm-intel-next-2020-04-17' of git://anongit.freedesktop.or…

…g/drm/drm-intel into drm-next

UAPI Changes:

- drm/i915/perf: introduce global sseu pinning
  Allow userspace to request at perf/OA open full SSEU configuration
  on the system to be able to benchmark 3D workloads, at the cost of not
  being able to run media workloads. (Lionel)

  Userspace changes: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4021

- drm/i915/perf: add new open param to configure polling of OA buffer
  Let application choose how often the OA buffer should be checked on
  the CPU side for data availability for choosig between CPU overhead
  and realtime nature of data.

  Userspace changes: https://patchwork.freedesktop.org/series/74655/

  (i915 perf recorder is a tool to capture i915 perf data for viewing
  in GPUVis.)

- drm/i915/perf: remove generated code
  Removal of the machine generated perf/OA test configurations from i915.
  Used by Mesa v17.1-18.0, and shortly replaced by userspace supplied OA
  configurations. Removal of configs causes affected Mesa versions to
  fall back to earlier kernel behaviour (potentially missing metrics).
  (Lionel)

Cross-subsystem Changes:

- Backmerge of drm-next

- Includes tag 'topic/phy-compliance-2020-04-08' from
  git://anongit.freedesktop.org/drm/drm-misc

Driver Changes:

- Fix for GitLab issue #27: Support 5k tiled dual DP display on SKL (Ville)
- Fix thesofproject#1719: Broken audio after
  S3 resume on JSL platforms. (Kai)
- Add new Tigerlake PCI IDs (Swathi D.)
- Add missing Tigerlake W/As (Matt R.)
- Extended Wa_2006604312 to EHL (Matt A)
- Add DPCD link_rate quirk for Apple 15" MBP 2017 (v3) (Mario)
- Make Wa_14010229206 apply to all Tigerlake steppings (Swathi d)
- Extend hotplug detect retry on TypeC connectors to 5 seconds (Imre)
- Yield the timeslice if caught waiting on a user semaphore (Chris)
- Limit the residual W/A batch to Haswell due to instability on IVB/BYT (Chris)
- TBT AUX should use TC power well ops on Tigerlake (Matt R)
- Update PMINTRMSK holding fw to make it effective for RPS (Francisco, Chris)
- Add YUV444 packed format support for skl+ (Stanislav)
- Invalidate OA TLB when closing perf stream to avoid corruption (Umesh)
- HDCP: fix Ri prime check done during link check (Oliver)
- Rearm heartbeat on sysfs interval change (Chris)
- Fix crtc nv12 etc. plane bitmasks for DPMS off (Ville)
- Treat idling as a RPS downclock event (Chris)
- Leave rps->cur_freq on unpark (Chris)
- Ignore short pulse when EDP panel powered off (Anshuman)
- Keep the engine awake until the next jiffie, to avoid ping-pong on
  moderate load (Chris)
- Select the deepest available parking mode for rc6 on IVB (Chris)
- Optimizations to direct submission execlist path (Chris)
- Avoid NULL pointer dereference at intel_read_infoframe() (Chris)
- Fix mode private_flags comparison at atomic_check (Uma, Ville)
- Use forced codec wake on all gen9+ platforms (Kai)
- Schedule oa_config after modifying the contexts (Chris, Lionel)
- Explicitly reset both reg and context runtime on GPU reset (Chris)
- Don't enable DDI IO power on a TypeC port in TBT mode (Imre)
- Fixes to TGL, ICL and EHL vswing tables (Jose)
- Fill all the unused space in the GGTT (Chris, imre)
- Ignore readonly failures when updating relocs (Chris)
- Attempt to find free space earlier for non-pinned VMAs (Chris)
- Only wait for GPU activity before unbinding a GGTT fence (Chris)
- Avoid data loss on small userspace perf OA polling (Ashutosh)
- Watch out for unevictable nodes during eviction (Matt A)
- Reinforce the barrier after GTT updates for Ironlake (Chris)

- Convert various parts of driver to use drm_device based logging (Wambui, Jani)
- Avoid dereferencing already closed context for engine (Chris)
- Enable non-contiguous pipe fusing (Anshuman)
- Add HW readout of Gamma LUT on ICL (Swati S.)
- Use explicit flag to mark unreachable intel_context (Chris)
- Cancel a hung context if already closed (Chris)
- Add DP VSC/HDR SDP data structures and write routines (Gwan-gyeong)
- Report context-is-closed prior to pinning at execbuf (Chris)
- Mark timeline->cacheline as destroyed after rcu grace period (Chris)
- Avoid live-lock with i915_vma_parked() (Chris)
- Avoid gem_context->mutex for simple vma lookup (Chris)
- Rely on direct submission to the queue (Chris)
- Configure DSI transcoder to operate in TE GATE command mode (Vandita)
- Add DI vblank calculation for command mode (Vandita)
- Disable periodic command mode if programmed by GOP (Vandita)
- Use private flags to indicate TE in cmd mode (Vandita)
- Make fences a nice-to-have for FBC on GEN9+ (Jose)
- Fix work queuing issue with mixed virtual engine/physical engine
  submissions (Chris)
- Drop final few uses of drm_i915_private.engine (Chris)
- Return early after MISSING_CASE for write_dp_sdp (Chris)
- Include port sync state in the state dump (Ville)
- ELSP workaround switching back to a completed context (Chris)
- Include priority info in trace_ports (Chris)
- Allow for different modes of interruptible i915_active_wait (Chris)
- Split eb_vma into its own allocation (Chris)
- Don't read perf head/tail pointers outside critical section (Lionel)
- Pause CS flow before execlists reset (Chris)
- Make fence revocation unequivocal (Chris)
- Drop cached obj->bind_count (Chris)
- Peek at the next submission for error interrupts (Chris)
- Utilize rcu iteration of context engines (Chris)
- Keep a per-engine request pool for power management ops (Chris)
- Refactor port sync code into normal modeset flow (Ville)
- Check current i915_vma.pin_count status first on unbind (Chris)
- Free request pool from virtual engines (Chris)
- Flush all the reloc_gpu batch (Chris)
- Make exclusive awaits on i915_active optional and allow async waits (Chris)
- Wait until the context is finally retired before releasing engines (Chris)

- Prefer '%ps' for printing function symbol names (Chris)
- Allow setting generic data pointer on intel GT debugfs (Andi)
- Constify DP link computation code more (Ville)
- Simplify MST master transcoder computation (Ville)
- Move TRANS_DDI_FUNC_CTL2 programming where it belongs (Ville)
- Move icl_get_trans_port_sync_config() into the DDI code (Ville)
- Add definitions for VRR registers and bits (Aditya)
- Refactor hardware fence code (Chris)
- Start passing latency as parameter to WM calculation (Stanislav)
- Kernel selftest and debug tracing improvements (Matt A, Chris, Mika)
- Fixes to CI found corner cases and lockdep splats (Chris)
- Overall fixes and refactoring to GEM code (Chris)
- Overall fixes and refactoring to display code (Ville)
- GuC/HuC code improvements (Daniele, Michal Wa)
- Static code checker fixes (Nathan, Ville, Colin, Chris)
- Fix spelling mistake (Chen)

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200417111548.GA15033@jlahtine-desk.ger.corp.intel.com

Documentation/gpu/i915.rst

@@ -391,19 +391,19 @@ Global GTT views
 GTT Fences and Swizzling
 ------------------------
 
-.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
+.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
    :internal:
 
 Global GTT Fence Handling
 ~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
+.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
    :doc: fence register handling
 
 Hardware Tiling and Swizzling Details
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
+.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
    :doc: tiling swizzling details
 
 Object Tiling IOCTLs

drivers/char/agp/intel-gtt.c

@@ -846,6 +846,7 @@ void intel_gtt_insert_page(dma_addr_t addr,
 			   unsigned int flags)
 {
 	intel_private.driver->write_entry(addr, pg, flags);
+	readl(intel_private.gtt + pg);
 	if (intel_private.driver->chipset_flush)
 		intel_private.driver->chipset_flush();
 }
@@ -871,7 +872,7 @@ void intel_gtt_insert_sg_entries(struct sg_table *st,
 			j++;
 		}
 	}
-	wmb();
+	readl(intel_private.gtt + j - 1);
 	if (intel_private.driver->chipset_flush)
 		intel_private.driver->chipset_flush();
 }
@@ -1105,6 +1106,7 @@ static void i9xx_cleanup(void)
 
 static void i9xx_chipset_flush(void)
 {
+	wmb();
 	if (intel_private.i9xx_flush_page)
 		writel(1, intel_private.i9xx_flush_page);
 }

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

@@ -2530,7 +2530,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
 	/* get phy test pattern and pattern parameters from DP receiver */
 	core_link_read_dpcd(
 			link,
-			DP_TEST_PHY_PATTERN,
+			DP_PHY_TEST_PATTERN,
 			&dpcd_test_pattern.raw,
 			sizeof(dpcd_test_pattern));
 	core_link_read_dpcd(

drivers/gpu/drm/drm_dp_helper.c

@@ -1238,6 +1238,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
 	{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
 	/* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
 	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
+	/* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
+	{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
 };
 
 #undef OUI
@@ -1533,3 +1535,97 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
 	return num_bpc;
 }
 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+/**
+ * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data)
+{
+	int err;
+	u8 rate, lanes;
+
+	err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
+	if (err < 0)
+		return err;
+	data->link_rate = drm_dp_bw_code_to_link_rate(rate);
+
+	err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
+	if (err < 0)
+		return err;
+	data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
+
+	if (lanes & DP_ENHANCED_FRAME_CAP)
+		data->enhanced_frame_cap = true;
+
+	err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
+	if (err < 0)
+		return err;
+
+	switch (data->phy_pattern) {
+	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
+		err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
+				       &data->custom80, sizeof(data->custom80));
+		if (err < 0)
+			return err;
+
+		break;
+	case DP_PHY_TEST_PATTERN_CP2520:
+		err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
+				       &data->hbr2_reset,
+				       sizeof(data->hbr2_reset));
+		if (err < 0)
+			return err;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
+
+/**
+ * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+				struct drm_dp_phy_test_params *data, u8 dp_rev)
+{
+	int err, i;
+	u8 link_config[2];
+	u8 test_pattern;
+
+	link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
+	link_config[1] = data->num_lanes;
+	if (data->enhanced_frame_cap)
+		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+	err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
+	if (err < 0)
+		return err;
+
+	test_pattern = data->phy_pattern;
+	if (dp_rev < 0x12) {
+		test_pattern = (test_pattern << 2) &
+			       DP_LINK_QUAL_PATTERN_11_MASK;
+		err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
+					 test_pattern);
+		if (err < 0)
+			return err;
+	} else {
+		for (i = 0; i < data->num_lanes; i++) {
+			err = drm_dp_dpcd_writeb(aux,
+						 DP_LINK_QUAL_LANE0_SET + i,
+						 test_pattern);
+			if (err < 0)
+				return err;
+		}
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);

drivers/gpu/drm/i915/Makefile

@@ -89,6 +89,7 @@ gt-y += \
 	gt/intel_engine_pool.o \
 	gt/intel_engine_user.o \
 	gt/intel_ggtt.o \
+	gt/intel_ggtt_fencing.o \
 	gt/intel_gt.o \
 	gt/intel_gt_irq.o \
 	gt/intel_gt_pm.o \
@@ -150,7 +151,6 @@ i915-y += \
 	  i915_buddy.o \
 	  i915_cmd_parser.o \
 	  i915_gem_evict.o \
-	  i915_gem_fence_reg.o \
 	  i915_gem_gtt.o \
 	  i915_gem.o \
 	  i915_globals.o \
@@ -164,14 +164,18 @@ i915-y += \
 
 # general-purpose microcontroller (GuC) support
 i915-y += gt/uc/intel_uc.o \
+	  gt/uc/intel_uc_debugfs.o \
 	  gt/uc/intel_uc_fw.o \
 	  gt/uc/intel_guc.o \
 	  gt/uc/intel_guc_ads.o \
 	  gt/uc/intel_guc_ct.o \
+	  gt/uc/intel_guc_debugfs.o \
 	  gt/uc/intel_guc_fw.o \
 	  gt/uc/intel_guc_log.o \
+	  gt/uc/intel_guc_log_debugfs.o \
 	  gt/uc/intel_guc_submission.o \
 	  gt/uc/intel_huc.o \
+	  gt/uc/intel_huc_debugfs.o \
 	  gt/uc/intel_huc_fw.o
 
 # modesetting core code
@@ -240,23 +244,6 @@ i915-y += \
 	display/vlv_dsi.o \
 	display/vlv_dsi_pll.o
 
-# perf code
-i915-y += \
-	oa/i915_oa_hsw.o \
-	oa/i915_oa_bdw.o \
-	oa/i915_oa_chv.o \
-	oa/i915_oa_sklgt2.o \
-	oa/i915_oa_sklgt3.o \
-	oa/i915_oa_sklgt4.o \
-	oa/i915_oa_bxt.o \
-	oa/i915_oa_kblgt2.o \
-	oa/i915_oa_kblgt3.o \
-	oa/i915_oa_glk.o \
-	oa/i915_oa_cflgt2.o \
-	oa/i915_oa_cflgt3.o \
-	oa/i915_oa_cnl.o \
-	oa/i915_oa_icl.o \
-	oa/i915_oa_tgl.o
 i915-y += i915_perf.o
 
 # Post-mortem debug and GPU hang state capture