Inconsistent use of latch vs flip-flop concepts

[aindree-2005]

Describe the bug

Inconsistent use of latch vs flip-flop concepts

To Reproduce

1. Open the CircuitVerse textbook section on sequential elements (D Flip Flop / SR Flip Flop).
2. Read the textual explanation and truth table describing the flip-flop behavior.
3. Compare the described behavior with:
   • The JavaScript simulator implementation.
   • The Verilog code generated/exported by the platform.
4. Observe that level-sensitive latch behavior, edge-triggered flip-flop behavior, and master–slave concepts are used interchangeably without clear explanation or distinction.

Expected behavior

The textbook should clearly and consistently explain:

• The difference between level-sensitive latches and edge-triggered flip-flops.
• What behavior CircuitVerse actually implements in simulation.
• How this behavior maps to the generated Verilog.

Concepts such as master–slave, edge-triggered, and level-sensitive operation should not be mixed without explicit clarification.

Screenshots

Not applicable. This is a conceptual/documentation issue rather than a UI rendering bug.

Desktop (please complete the following information):

• OS: Windows
• Browser: Chrome
• Version: v0/v1

Smartphone (please complete the following information):

Additional context

This issue can confuse learners and contributers without a background in digital electronics, as the same component is described textually as level-sensitive, implemented differently in simulation, and exported as edge-triggered logic in Verilog.
Clarifying these distinctions in the textbook would significantly improve conceptual correctness , code sanity and educational value.

[aindree-2005]

Is it an issue I can start contributing on?