16-bits-multi-cycle-CPU

A CPU Design project for the course "Application and Design of Digital Logic" at Glasgow College, UESTC.

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Please use Vivado 2017 to open 16_bits_multi_cycle_CPU.xpr.

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If you want to get more details about our CPU, please read 16-bits-multi-cycle-CPU Design Document.pdf

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1. Architecture diagram of our CPU

2. Specification

3. Input/Output table

4. Instruction set

5. Testbench on Xilinx Zynq7000 FPGA———Successful