Replace CPU APIs on Power

Issue: eclipse-omr#4339 Signed-off-by: Harry Yu <harryyu1994@gmail.com>
CAS-Atlantic · Jun 23, 2020 · 04d1d89 · 04d1d89
1 parent a50cf4d
commit 04d1d89
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Showing 17 changed files with 314 additions and 168 deletions.
diff --git a/compiler/env/OMRCPU.cpp b/compiler/env/OMRCPU.cpp
@@ -87,7 +87,11 @@ OMR::CPU::CPU() :
 #endif
    }
 
-OMR::CPU::CPU(const OMRProcessorDesc& processorDescription) : 
+OMR::CPU::CPU(const OMRProcessorDesc& processorDescription) :
+   _processor(TR_NullProcessor),
+   _endianness(TR::endian_unknown),
+   _majorArch(TR::arch_unknown),
+   _minorArch(TR::m_arch_none),
    _processorDescription(processorDescription)
    {
 #ifdef OMR_ENV_LITTLE_ENDIAN
@@ -137,7 +141,6 @@ OMR::CPU::CPU(const OMRProcessorDesc& processorDescription) :
 #endif
    }
 
-
 TR::CPU *
 OMR::CPU::self()
    {
@@ -156,13 +159,6 @@ OMR::CPU::detect(OMRPortLibrary * const omrPortLib)
    return TR::CPU(processorDescription);
    }
 
-bool
-OMR::CPU::is(OMRProcessorArchitecture p)
-   {
-   TR_ASSERT_FATAL(TR::Compiler->omrPortLib != NULL, "Should not be calling this OMR level API without a valid port library pointer. Perhaps we did not initialize the port library properly?\n");
-   return _processorDescription.processor == p;
-   }
-
 bool
 OMR::CPU::supportsFeature(uint32_t feature)
    {

diff --git a/compiler/env/OMRCPU.hpp b/compiler/env/OMRCPU.hpp
@@ -138,6 +138,7 @@ class OMR_EXTENSIBLE CPU
    void setMinorArch(TR::MinorArchitecture a) { _minorArch = a; }
    bool isI386() { return _minorArch == TR::m_arch_i386; }
    bool isAMD64() { return _minorArch == TR::m_arch_amd64; }
+   void applyUserOptions() {}
 
    /** 
     * @brief Determines whether the Transactional Memory (TM) facility is available on the current processor.
@@ -150,7 +151,7 @@ class OMR_EXTENSIBLE CPU
     * @param[in] p : the input processor type
     * @return true when current processor is the same as the input processor type
     */
-   bool is(OMRProcessorArchitecture p);
+   bool is(OMRProcessorArchitecture p) { return _processorDescription.processor == p; }
 
    /**
     * @brief Determines whether current processor is equal or newer than the input processor type
@@ -170,7 +171,7 @@ class OMR_EXTENSIBLE CPU
     * @brief Retrieves current processor's processor description
     * @return processor description which includes processor type and processor features
     */
-   const OMRProcessorDesc & getProcessorDescription() const { return _processorDescription; }
+   OMRProcessorDesc getProcessorDescription() { return _processorDescription; }
 
    /** 
     * @brief Determines whether current processor supports the input processor feature

diff --git a/compiler/p/codegen/BinaryEvaluator.cpp b/compiler/p/codegen/BinaryEvaluator.cpp
@@ -204,7 +204,7 @@ TR::Register *OMR::Power::TreeEvaluator::iaddEvaluator(TR::Node *node, TR::CodeG
 
    TR::Node *firstChild = node->getFirstChild();
 
-  if (cg->comp()->target().cpu.id() >= TR_PPCp9 &&
+   if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9)  &&
       firstChild->getOpCodeValue() == TR::imul &&
       firstChild->getReferenceCount() == 1 &&
       firstChild->getRegister() == NULL)
@@ -508,7 +508,7 @@ TR::Register *OMR::Power::TreeEvaluator::laddEvaluator(TR::Node *node, TR::CodeG
          return trgReg;
          }
 
-      if (cg->comp()->target().cpu.id() >= TR_PPCp9 &&
+      if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9) &&
           !setsOrReadsCC &&
           (node->getOpCodeValue() == TR::ladd || node->getOpCodeValue() == TR::aladd) &&
           firstChild->getOpCodeValue() == TR::lmul &&
@@ -1621,7 +1621,7 @@ static TR::Register *signedIntegerDivisionOrRemainderAnalyser(TR::Node
             generateTrg1Src1Instruction(cg, TR::InstOpCode::neg, node, trgReg, trgReg);
          }
       }
-   else if (cg->comp()->target().cpu.id() >= TR_PPCp9 && isRemainder)
+   else if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9) && isRemainder)
       {
       if (divisorReg == NULL)
          divisorReg = cg->evaluate(node->getSecondChild());
@@ -2078,7 +2078,7 @@ strengthReducingLongDivideOrRemainder32BitMode(TR::Node *node,      TR::CodeGene
 
          if (isRemainder)
             {
-            if (cg->comp()->target().cpu.id() >= TR_PPCp9)
+            if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
                {
                generateTrg1Src2Instruction(cg, TR::InstOpCode::moduw, node, dr_l, dd_l, dr_l);
                }
@@ -2099,7 +2099,7 @@ strengthReducingLongDivideOrRemainder32BitMode(TR::Node *node,      TR::CodeGene
 
    TR_RuntimeHelper helper;
 
-   if (cg->comp()->target().cpu.id() >= TR_PPCp7 && !isDivisorImpossible32Bit)
+   if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) && !isDivisorImpossible32Bit)
       helper = isSignedOp ? TR_PPClongDivideEP : TR_PPCunsignedLongDivideEP;
    else
       helper = isSignedOp ? TR_PPClongDivide : TR_PPCunsignedLongDivide;
@@ -2154,7 +2154,7 @@ TR::Register *OMR::Power::TreeEvaluator::iremEvaluator(TR::Node *node, TR::CodeG
          {
          TR::Register *divisorReg = cg->evaluate(secondChild);
          trgReg = cg->allocateRegister();
-         if(cg->comp()->target().cpu.id() >= TR_PPCp9)
+         if(cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
             {
             generateTrg1Src2Instruction(cg, TR::InstOpCode::modsw, node, trgReg, dividendReg, divisorReg);
             }
@@ -2210,7 +2210,7 @@ TR::Register *OMR::Power::TreeEvaluator::iremEvaluator(TR::Node *node, TR::CodeG
             generateConditionalBranchInstruction(cg, TR::InstOpCode::beq, node, doneLabel, condReg);
             cg->stopUsingRegister(condReg);
             }
-         if(cg->comp()->target().cpu.id() >= TR_PPCp9)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
             {
             generateTrg1Src2Instruction(cg, TR::InstOpCode::modsw, node, trgReg, dividendReg, divisorReg);
             }
@@ -2250,7 +2250,7 @@ TR::Register *lrem64Evaluator(TR::Node *node, TR::CodeGenerator *cg)
          {
          TR::Register *divisorReg = cg->evaluate(secondChild);
          trgReg = cg->allocateRegister();
-         if(cg->comp()->target().cpu.id() >= TR_PPCp9)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
             {
             generateTrg1Src2Instruction(cg, TR::InstOpCode::modsd, node, trgReg, dividendReg, divisorReg);
             }
@@ -2306,7 +2306,7 @@ TR::Register *lrem64Evaluator(TR::Node *node, TR::CodeGenerator *cg)
             generateConditionalBranchInstruction(cg, TR::InstOpCode::beq, node, doneLabel, condReg);
             cg->stopUsingRegister(condReg);
             }
-         if (cg->comp()->target().cpu.id() >= TR_PPCp9)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
             {
             generateTrg1Src2Instruction(cg, TR::InstOpCode::modsd, node, trgReg, dividendReg, divisorReg);
             }
@@ -2350,7 +2350,7 @@ TR::Register *OMR::Power::TreeEvaluator::lremEvaluator(TR::Node *node, TR::CodeG
 static bool isPower9Extswsli(TR::CodeGenerator *cg, TR::Node *node)
    {
    static bool disableExtswsli = feGetEnv("TR_DisableExtswsli");
-   if (disableExtswsli || cg->comp()->target().cpu.id() < TR_PPCp9)
+   if (disableExtswsli || !cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
       return false;
 
    TR::Node *lhs = node->getFirstChild();

diff --git a/compiler/p/codegen/ControlFlowEvaluator.cpp b/compiler/p/codegen/ControlFlowEvaluator.cpp
@@ -2497,7 +2497,7 @@ TR::Register *OMR::Power::TreeEvaluator::lcmpEvaluator(TR::Node *node, TR::CodeG
       {
       if (secondChild->getOpCode().isLoadConst() && secondChild->getLongInt()==0)
          {
-         if (cg->comp()->target().cpu.id() >= TR_PPCp9)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
             {
             TR::Register *condReg = cg->allocateRegister(TR_CCR);
             generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::cmpi8, node, condReg, src1Reg, 0);
@@ -2518,7 +2518,7 @@ TR::Register *OMR::Power::TreeEvaluator::lcmpEvaluator(TR::Node *node, TR::CodeG
       else
          {
          TR::Register *src2Reg = cg->evaluate(secondChild);
-         if (cg->comp()->target().cpu.id() >= TR_PPCp9)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
             {
             TR::Register *condReg = cg->allocateRegister(TR_CCR);
             generateTrg1Src2Instruction(cg, TR::InstOpCode::cmp8, node, condReg, src1Reg, src2Reg);

diff --git a/compiler/p/codegen/FPTreeEvaluator.cpp b/compiler/p/codegen/FPTreeEvaluator.cpp
@@ -116,7 +116,7 @@ TR::Register *OMR::Power::TreeEvaluator::fbits2iEvaluator(TR::Node *node, TR::Co
       }
    else
       {
-      floatReg = cg->comp()->target().cpu.id() >= TR_PPCp8 ? cg->gprClobberEvaluate(child) : cg->evaluate(child);
+      floatReg = cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) ? cg->gprClobberEvaluate(child) : cg->evaluate(child);
       generateMvFprGprInstructions(cg, node, fpr2gprSp, cg->comp()->target().is64Bit(),target, floatReg);
       childEval = floatReg == child->getRegister();
       cg->decReferenceCount(child);
@@ -204,7 +204,7 @@ TR::Register *OMR::Power::TreeEvaluator::lbits2dEvaluator(TR::Node *node, TR::Co
       else
          {
          TR::Register *longReg = cg->evaluate(child);
-         if (cg->comp()->target().cpu.id() >= TR_PPCp8)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8))
             {
             TR::Register * tmp1 = cg->allocateRegister(TR_FPR);
             generateMvFprGprInstructions(cg, node, gpr2fprHost32, false, target, longReg->getHighOrder(), longReg->getLowOrder(), tmp1);
@@ -273,7 +273,7 @@ TR::Register *OMR::Power::TreeEvaluator::dbits2lEvaluator(TR::Node *node, TR::Co
          {
          highReg = cg->allocateRegister();
          lowReg = cg->allocateRegister();
-         if (cg->comp()->target().cpu.id() >= TR_PPCp8)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8))
             {
             TR::Register * tmp1 = cg->allocateRegister(TR_FPR);
             generateMvFprGprInstructions(cg, node, fpr2gprHost32, false, highReg, lowReg, doubleReg, tmp1);
@@ -650,7 +650,7 @@ TR::Register *OMR::Power::TreeEvaluator::vsplatsEvaluator(TR::Node *node, TR::Co
       TR::Register *tempReg = cg->evaluate(child);
       TR::Register *resReg = cg->allocateRegister(TR_VRF);
 
-      if (!disableDirectMove && cg->comp()->target().cpu.id() >= TR_PPCp8 && cg->comp()->target().cpu.getPPCSupportsVSX())
+      if (!disableDirectMove && cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) && cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX))
          {
          generateMvFprGprInstructions(cg, node, gprLow2fpr, false, resReg, tempReg);
          generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::xxspltw, node, resReg, resReg, 0x1);
@@ -682,7 +682,7 @@ TR::Register *OMR::Power::TreeEvaluator::vsplatsEvaluator(TR::Node *node, TR::Co
       TR::Register *srcReg = cg->evaluate(child);
       TR::Register *trgReg = cg->allocateRegister(TR_VRF);
 
-      if (!disableDirectMove && cg->comp()->target().cpu.id() >= TR_PPCp8 && cg->comp()->target().cpu.getPPCSupportsVSX())
+      if (!disableDirectMove && cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) && cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX))
          {
          if (cg->comp()->target().is64Bit())
             {
@@ -1390,7 +1390,7 @@ TR::Register *OMR::Power::TreeEvaluator::int2dbl(TR::Node * node, TR::Register *
          }
       else
          {
-         if (cg->comp()->target().cpu.id() >= TR_PPCp6 && node->getOpCodeValue() != TR::iu2f && node->getOpCodeValue() != TR::iu2d)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6) && node->getOpCodeValue() != TR::iu2f && node->getOpCodeValue() != TR::iu2d)
             generateMvFprGprInstructions(cg, node, gprLow2fpr, false, trgReg, srcReg);
          else
             {
@@ -1401,7 +1401,7 @@ TR::Register *OMR::Power::TreeEvaluator::int2dbl(TR::Node * node, TR::Register *
             else
                generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::srawi, node, tempReg, srcReg, 31);
 
-            if (cg->comp()->target().cpu.id() >= TR_PPCp8)
+            if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8))
                {
                TR::Register * tmp1 = cg->allocateRegister(TR_FPR);
                generateMvFprGprInstructions(cg, node, gpr2fprHost32, false, trgReg, tempReg, srcReg, tmp1);
@@ -1412,7 +1412,7 @@ TR::Register *OMR::Power::TreeEvaluator::int2dbl(TR::Node * node, TR::Register *
             cg->stopUsingRegister(tempReg);
             }
          }
-      if ((cg->comp()->target().cpu.id() >= TR_PPCp7) &&
+      if ((cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7)) &&
           (node->getOpCodeValue() == TR::i2f || node->getOpCodeValue() == TR::iu2f))
          {
          // Generate the code to produce the float result here, setting the register flag is done afterwards
@@ -1460,9 +1460,9 @@ TR::Register *OMR::Power::TreeEvaluator::i2fEvaluator(TR::Node *node, TR::CodeGe
    TR::Register *tempReg;
    TR::Register *trgReg;
 
-   if (((cg->comp()->target().cpu.id() >= TR_PPCp7 &&
+   if (((cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) &&
        (node->getOpCodeValue() == TR::iu2f && (child->getOpCodeValue() == TR::iuload || child->getOpCodeValue() == TR::iuloadi))) ||
-       (cg->comp()->target().cpu.id() >= TR_PPCp6 &&
+       (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6) &&
        (node->getOpCodeValue() == TR::i2f && (child->getOpCodeValue() == TR::iload || child->getOpCodeValue() == TR::iloadi)))) &&
        child->getReferenceCount() == 1 && child->getRegister() == NULL &&
        !(child->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP()))
@@ -1474,7 +1474,7 @@ TR::Register *OMR::Power::TreeEvaluator::i2fEvaluator(TR::Node *node, TR::CodeGe
       if (node->getOpCodeValue() == TR::i2f)
          {
          generateTrg1MemInstruction(cg, TR::InstOpCode::lfiwax, node, tempReg, tempMR);
-         if (cg->comp()->target().cpu.id() >= TR_PPCp7)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7))
             {
             generateTrg1Src1Instruction(cg, TR::InstOpCode::fcfids, node, trgReg, tempReg);
             }
@@ -1508,9 +1508,9 @@ TR::Register *OMR::Power::TreeEvaluator::i2dEvaluator(TR::Node *node, TR::CodeGe
    TR::Node     *child      = node->getFirstChild();
    TR::Register *trgReg;
 
-   if (((cg->comp()->target().cpu.id() >= TR_PPCp7 &&
+   if (((cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) &&
        (node->getOpCodeValue() == TR::iu2d && (child->getOpCodeValue() == TR::iuload || child->getOpCodeValue() == TR::iuloadi))) ||
-       (cg->comp()->target().cpu.id() >= TR_PPCp6 &&
+       (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6) &&
        node->getOpCodeValue() == TR::i2d && (child->getOpCodeValue() == TR::iload || child->getOpCodeValue() == TR::iloadi))) &&
        child->getReferenceCount()==1 &&
        child->getRegister() == NULL &&
@@ -1555,7 +1555,7 @@ TR::Register *OMR::Power::TreeEvaluator::long2dbl(TR::Node *node, TR::CodeGenera
          generateMvFprGprInstructions(cg, node, gpr2fprHost64, false, trgReg, srcReg);
       else
          {
-         if (cg->comp()->target().cpu.id() >= TR_PPCp8)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8))
             {
             TR::Register * tmp1 = cg->allocateRegister(TR_FPR);
             generateMvFprGprInstructions(cg, node, gpr2fprHost32, false, trgReg, srcReg->getHighOrder(), srcReg->getLowOrder(), tmp1);
@@ -1609,14 +1609,14 @@ TR::Register *OMR::Power::TreeEvaluator::long2float(TR::Node *node, TR::CodeGene
    TR::Register *srcReg  = cg->evaluate(child);
    TR::Register *trgReg     = cg->allocateSinglePrecisionRegister(TR_FPR);
 
-   if (cg->comp()->target().cpu.id() >= TR_PPCp7 &&
+   if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) &&
       (cg->is64BitProcessor() || (cg->comp()->compileRelocatableCode() && cg->comp()->target().is64Bit())))
       {
       if (cg->comp()->target().is64Bit())
          generateMvFprGprInstructions(cg, node, gpr2fprHost64, false, trgReg, srcReg);
       else
          {
-         if (cg->comp()->target().cpu.id() >= TR_PPCp8)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8))
             {
             TR::Register * tmp1 = cg->allocateRegister(TR_FPR);
             generateMvFprGprInstructions(cg, node, gpr2fprHost32, false, trgReg, srcReg->getHighOrder(), srcReg->getLowOrder(), tmp1);
@@ -1697,7 +1697,7 @@ TR::Register *OMR::Power::TreeEvaluator::l2fEvaluator(TR::Node *node, TR::CodeGe
    {
    TR::Register *trgReg;
    TR::Node     *child      = node->getFirstChild();
-   if (cg->comp()->target().cpu.id() >= TR_PPCp7 &&
+   if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) &&
        node->getOpCodeValue() == TR::l2f &&
        (child->getOpCodeValue() == TR::lload || child->getOpCodeValue() == TR::lloadi) &&
        child->getReferenceCount()==1 &&
@@ -1725,8 +1725,7 @@ TR::Register *OMR::Power::TreeEvaluator::l2dEvaluator(TR::Node *node, TR::CodeGe
    {
    TR::Register *trgReg;
    TR::Node     *child      = node->getFirstChild();
-   if (
-       cg->comp()->target().cpu.id() >= TR_PPCp7 &&
+   if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) &&
        node->getOpCodeValue() == TR::l2d &&
        (child->getOpCodeValue() == TR::lload || child->getOpCodeValue() == TR::lloadi) &&
        child->getReferenceCount()==1 &&
@@ -2033,7 +2032,7 @@ TR::Register *OMR::Power::TreeEvaluator::dcmpneEvaluator(TR::Node *node, TR::Cod
 TR::Register *OMR::Power::TreeEvaluator::dcmpltEvaluator(TR::Node *node, TR::CodeGenerator *cg)
    {
    int64_t imm = 0;
-   if (cg->comp()->target().cpu.id() >= TR_PPCp9)
+   if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
       {
       imm = (TR::RealRegister::CRCC_GT <<  TR::RealRegister::pos_RT | TR::RealRegister::CRCC_LT <<  TR::RealRegister::pos_RA | TR::RealRegister::CRCC_LT << TR::RealRegister::pos_RB);
       }
@@ -2282,7 +2281,7 @@ static TR::Register *compareFloatAndSetOrderedBoolean(TR::InstOpCode::Mnemonic b
       cfop->addTargetRegister(trgReg);
       cfop->addSourceRegister(src1Reg);
       cfop->addSourceRegister(src2Reg);
-      if (cg->comp()->target().cpu.id() >= TR_PPCp9 && branchOp2 == TR::InstOpCode::bad && imm != 0)
+      if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9) && branchOp2 == TR::InstOpCode::bad && imm != 0)
          {
          cfop->addSourceImmediate(imm);
          }