Update BHG_FP_clk_divider.v

Add files via upload

   1.2a - Added a protection for when the integer divider has less than 2 bits.
   1.2b- Added a compilation $error and $stop with instructions if the user supplies inoperable CLK_HZ parameters.
   1.1 - Fixed a bug with some Modelsim versions where its 'Compile/Compile Options/Language Syntax' is set to 'Use Verilog 2001' instead of 'Default'.
   1.0 - Initial release.

Update README.md

Update README.md