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Achievement: Pull SharkAchievement: Quickdraw

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Bhavin-umatiya/README.md

R&D Hardware Intern @Oizom | Linux Foundation Contributor

I fell in love with hardware the day I watched a signal propagate through a gate-level netlist I'd designed—and realized I was watching logic think. My mission is to design silicon that ships.

Portfolio LinkedIn Email

💻 Tech Stack & Tools

SystemVerilog Verilog VHDL UVM
C Python Zephyr ROS 2
Vivado Quartus ModelSim STM32

🚀 Top Engineering Projects

Project Description Tech Stack
💻 8-bit Pipelined CPU Designed an end-to-end 5-stage pipelined processor (Fetch to Write-Back) with hazard detection and custom ALU. Verilog Vivado ModelSim
⚡ 64-bit Carry Save Adder High-performance arithmetic unit designed in RTL and hardware-validated on an Intel DE2 Cyclone II FPGA. Verilog Quartus FPGA
🔒 Secure Firmware Bootloader Bare-metal embedded C bootloader featuring checksum-based integrity validation and dual-bank flash architecture. Embedded C STM32 UART
🧠 Neuromorphic SNN Accelerator (In Progress) Spiking Neural Network hardware accelerator with Leaky Integrate-and-Fire neurons. SystemVerilog Xilinx
🤖 AI-VLSI Co-Design Agentic 3-agent AI pipeline automating synthesizable RTL generation from natural language specs. SystemVerilog Python LLMs

🌍 Open Source Contributor

As an active contributor to the Linux Foundation, I believe in writing production-grade, review-ready code:

  • 🛠️ Zephyr RTOS: Contributed POSIX compliance fixes and passed strict Twister/checkpatch CI pipelines.
  • 🏎️ ROS 2: Shipped merged PRs in ros2_controllers used by robotics teams worldwide.

Pinned Loading

  1. 64bit-carry-save-adder-fpga-de2 64bit-carry-save-adder-fpga-de2 Public

    Carry Save Adder on FPGA (DE2 Kit) • Designed a 64-bit Carry Save Adder (CSA) using Verilog HDL. • Simulated in ModelSim and synthesized using Quartus; output displayed via 7-segment display.

    Verilog

  2. pipelined-8bit-cpu-verilog pipelined-8bit-cpu-verilog Public

    Design and Implementation of an 8-bit CPU in Verilog

    Verilog

  3. secure-bootloader-stm32-checksum secure-bootloader-stm32-checksum Public

    secure firmware bootloader STM32 Nucleo bord

    C

  4. zephyrproject-rtos/zephyr zephyrproject-rtos/zephyr Public

    Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

    C 15.3k 9.2k

  5. ros2_controllers ros2_controllers Public

    Forked from ros-controls/ros2_controllers

    Generic robotic controllers to accompany ros2_control

    C++

  6. async-fifo-uvm-verification async-fifo-uvm-verification Public

    SystemVerilog