🎰 Vending Machine Controller - Mealy FSM Implementation

A synthesizable RTL design of a vending machine controller using Mealy FSM architecture

Features • Architecture • State Machine • Simulation • FPGA Results • Usage • Author

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📖 Table of Contents

• Project Overview
• Key Specifications
• Features
• Architecture
  • Module Interface
  • RTL Implementation Highlights
• State Machine Design
  • State Encoding
  • State Transition Diagram
  • Comprehensive State Transition Table
• Repository Structure
• Simulation
  • Test Scenarios
  • Simulation Results Preview
• FPGA Implementation Results
  • Resource Utilization
  • Timing Analysis
  • Power Consumption
  • Implementation Visuals
• Usage
  • Prerequisites
  • Quick Start
  • Synthesis Guidelines
• Design Highlights
  • Why This Implementation Stands Out
  • Technical Excellence
• Author

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📋 Project Overview

This project implements a fully synthesizable vending machine controller using Verilog HDL, designed as a Mealy Finite State Machine (FSM). The controller manages coin acceptance, change calculation, and transaction cancellation with robust state management and clean RTL design principles.

📋 Key Specifications

Parameter	Value / Type
Item Price	15 cents
Accepted Coins	Nickel (5¢), Dime (10¢)
FSM Architecture	3-State Mealy Machine
State Bits	2 ([1:0])
Reset Type	Active-Low Asynchronous
HDL Standard	Verilog-2001

✨ Features

• High Performance: The Mealy FSM architecture ensures a minimal latency of a single clock cycle for all outputs.
• Robust & Synthesizable: Written in a strict two-process style with default assignments to guarantee a latch-free, reliable synthesis result for both FPGAs and ASICs.
• Intelligent Change Calculation: The logic automatically handles all overpayment scenarios and dispenses the correct change.
• Full User Control: A dedicated cancel input allows the user to abort the transaction and receive a full refund at any point.
• Comprehensive Verification: The design is validated by a self-checking testbench that covers all state transitions and edge cases.

🏗️ Architecture

Module Interface

module vending_machine_mealy(
  input  wire clk,          // System clock
  input  wire rst,          // Active-low async reset
  input  wire nickel,       // 5¢ coin insert signal
  input  wire dime,         // 10¢ coin insert signal
  input  wire cancel,       // Transaction cancel
  output reg  vend,         // Item dispense signal
  output reg  change_5C,    // 5¢ change return
  output reg  change_10C    // 10¢ change return
);

RTL Implementation Highlights

The design follows industry-standard two-process FSM methodology:

1. Sequential Process: State register updates on clock edge
2. Combinational Process: Next-state and output logic computation
3. Default Assignments: Prevents unintended latch synthesis
4. Complete Case Coverage: Ensures deterministic behavior

🔄 State Machine Design

State Encoding

State	Encoding	Amount	Description
S_0C	2'b00	0¢	Initial/Idle state
S_5C	2'b01	5¢	Five cents accumulated
S_10C	2'b10	10¢	Ten cents accumulated

State Transition Diagram

stateDiagram-v2
    direction TB
    
    [*] --> S_0C : !rst
    
    S_0C --> S_5C : N/000
    S_0C --> S_10C : D/000
    S_0C --> S_0C : C/000
    
    S_5C --> S_10C : N/000
    S_5C --> S_0C : D/100
    S_5C --> S_0C : C/010
    
    S_10C --> S_0C : N/100
    S_10C --> S_0C : D/110
    S_10C --> S_0C : C/001

Loading

Comprehensive State Transition Table

Present State	Inputs	Next State	Outputs
ps[1:0]	{dime, nickel, cancel}	ns[1:0]	{vend, change_5C, change_10C}
2'b00 (S_0C)	3'b000 (none)	2'b00 (S_0C)	3'b000
2'b00 (S_0C)	3'b001 (cancel)	2'b00 (S_0C)	3'b000
2'b00 (S_0C)	3'b010 (nickel)	2'b01 (S_5C)	3'b000
2'b00 (S_0C)	3'b100 (dime)	2'b10 (S_10C)	3'b000
2'b01 (S_5C)	3'b000 (none)	2'b01 (S_5C)	3'b000
2'b01 (S_5C)	3'b001 (cancel)	2'b00 (S_0C)	3'b010
2'b01 (S_5C)	3'b010 (nickel)	2'b10 (S_10C)	3'b000
2'b01 (S_5C)	3'b100 (dime)	2'b00 (S_0C)	3'b100
2'b10 (S_10C)	3'b000 (none)	2'b10 (S_10C)	3'b000
2'b10 (S_10C)	3'b001 (cancel)	2'b00 (S_0C)	3'b001
2'b10 (S_10C)	3'b010 (nickel)	2'b00 (S_0C)	3'b100
2'b10 (S_10C)	3'b100 (dime)	2'b00 (S_0C)	3'b110
2'b11 (Unused)	3'bxxx	2'b00 (S_0C)	3'b000

*Note: The table assumes only one input is active at a time.

Output format: {vend, change_5C, change_10C}

📁 Repository Structure

vending-machine-rtl/
│
├── 📄 vending_machine_mealy.v          # Main RTL module
├── 📄 vending_machine_mealy_tb.v       # Comprehensive testbench
├── 📄 constraints.xdc                  # Timing constraints file
├── 📄 rtl_schematic.pdf                # RTL schematic view
├── 📄 synthesized_schematic.pdf        # Post-synthesis schematic
├── 📄 Power_Analysis_Result.png        # Power consumption report
├── 📄 Behavioral_Simulation.png        # Simulation waveforms
├── 📄 fpga_floorplan_overview.png      # Complete FPGA floorplan
├── 📄 fpga_floorplan_detailed.png      # Detailed placement view
├── 📄 fpga_slice_implementation.png    # Slice-level implementation
└── 📄 README.md                        # This documentation

🧪 Simulation

Test Scenarios

The testbench validates critical operational scenarios:

Test #	Description	Input Sequence	Expected Output
1	Exact payment (N+D)	5¢ → 10¢	Vend item
2	Exact payment (D+N)	10¢ → 5¢	Vend item
3	Overpayment	10¢ → 10¢	Vend + 5¢ change
4	Cancel after nickel	5¢ → Cancel	Return 5¢
5	Cancel after dime	10¢ → Cancel	Return 10¢

Simulation Results Preview

=== Vending Machine Test Started ===
Item Price: 15 cents

Test 1: Nickel + Dime = 15 cents
 <>Inserting Nickel (5c)...
Time=35 | State=01 | vend=0 change_5C=0 change_10C=0
 <>Inserting Dime (10c)...
Time=55 | State=00 | vend=1 change_5C=0 change_10C=0
  >>> Item dispensed

Test 3: Dime + Dime = 20 cents (expect 5c change)
 <>Inserting Dime (10c)...
Time=135 | State=10 | vend=0 change_5C=0 change_10C=0
 <>Inserting Dime (10c)...
Time=155 | State=00 | vend=1 change_5C=1 change_10C=0
  >>> Item dispensed with 5c change

FPGA Implementation Results (Artix-7 xc7a35tcpg236-1)

Resource Utilization

Resource	Used	Available	Utilization %
Slice LUTs	5	20,800	0.024%
Slice Registers	2	41,600	0.005%
Bonded IOB	8	106	7.55%
BUFGCTRL	1	32	3.13%

Timing Analysis

Parameter	Value	Status
Target Frequency	100 MHz	✅ Met
Setup Slack (WNS)	+0.592 ns	✅ Positive
Hold Slack (WHS)	+0.146 ns	✅ Positive

Power Consumption

Parameter	Value
Total On-Chip Power	72 mW
Dynamic Power	2 mW (3%)
Static Power	70 mW (97%)
Junction Temperature	25.4°C

Implementation Visuals

• RTL/Synthesized Schematics: Show the logical design structure and gate-level implementation
• Power Analysis: Demonstrates ultra-low power operation (72mW total) suitable for battery-powered applications
• FPGA Floorplan: Physical placement visualization on Artix-7 device showing efficient resource utilization
• Slice Implementation: Detailed view of actual LUT and flip-flop usage at the hardware level

🚀 Usage

Prerequisites

• Verilog simulator (Icarus Verilog, ModelSim, Vivado, VCS)
• GTKWave or similar waveform viewer (optional)
• Synthesis tool for FPGA/ASIC implementation (optional)

Quick Start

Using Icarus Verilog (Open Source)

# Clone the repository
git clone https://github.com/AyushVerma17/vending-machine-rtl.git
(Make sure you are in the same directory in which the project is)

# Compile the design
iverilog -o vend_mealy vending_machine_mealy.v vending_machine_mealy_tb.v

# Run simulation
vvp vend_mealy

# View waveforms (optional)
gtkwave vending_machine.vcd &

Using ModelSim/QuestaSim

# Create work library
vlib work

# Compile sources
vlog vending_machine_mealy.v vending_machine_mealy_tb.v

# Start simulation
vsim -novopt work.vending_machine_mealy_tb

# Add signals to waveform
add wave -recursive *

# Run simulation
run -all

Using Vivado

# 📁 Create project
create_project -> vending_machine(Project_name) -> RTL Project (Do not specify resources at this time)
Parts -> category (General Purpose) -> Family(Artix-7) -> Package(cpg236) -> Speed(-1) -> xc7a35tcpg236-1

# ➕ Add sources
Add Sources -> Add or create design sources -> Add_files -> vending_machine_mealy.v -> Save
Add Sources -> Add or create simulation sources -> Add_files -> vending_machine_mealy_tb.v -> Save
Add Sources -> Add or create constraints -> Create File -> constraints.xdc -> Add timing constraints

# 📝 Add timing constraints to constraints.xdc file:
create_clock -period 10.0 -name sys_clk [get_ports clk]
set_input_delay -clock sys_clk 2.0 [get_ports {rst nickel dime cancel}]
set_output_delay -clock sys_clk 2.0 [get_ports {vend change_5C change_10C}]

# 👁️ RTL_View
RTL ANALYSIS -> Open Elaborated Design  

# ▶️ Run simulation
SIMULATION -> Run Simulation -> Run Behavioral Simulation -> Check waveform window

# 🔧 Complete FPGA Implementation Flow
SYNTHESIS -> Run Synthesis -> Wait for completion
IMPLEMENTATION -> Run Implementation -> Wait for completion

# 📊 Generate comprehensive reports
Reports -> Implementation -> Report Timing Summary -> Generate timing analysis
Reports -> Implementation -> Report Utilization -> Generate resource usage report  
Reports -> Implementation -> Report Power -> Configure power settings -> Generate power report

# 🗺️ View physical implementation
Layout -> Device -> View FPGA floorplan and placement
Layout -> Floorplanning -> Zoom in for detailed slice implementation

# 📈 Key reports to check:
- Timing: Setup/Hold slack should be positive
- Utilization: Verify efficient resource usage  
- Power: Check total on-chip power consumption
- Implementation: Confirm "All user specified timing constraints are met"

Synthesis Guidelines

Target Specifications:

• Target frequency: 100 MHz (10ns period)
• Timing constraints: Defined in constraints.xdc
• Verified platform: Artix-7 xc7a35tcpg236-1
• Process corner: Commercial grade (-1 speed)

Validation Results:

• ✅ No latch inference
• ✅ Complete case statements
• ✅ Synchronous design principles
• ✅ Timing closure achieved (+0.592ns setup slack)
• ✅ Hold timing met (+0.146ns hold slack)
• ✅ All user-specified constraints satisfied

🔍 Design Highlights

Why This Implementation Stands Out

1. Clean Coding Style: Follows industry-standard RTL coding guidelines
2. Robust Design: Handles all edge cases with proper default assignments
3. Maintainable: Well-commented code with clear separation of concerns
4. Testable: Comprehensive testbench with task-based testing methodology
5. Synthesizable: Optimized for both FPGA and ASIC implementation

Technical Excellence

• No Implicit Latches: Default assignments in combinational blocks
• Timing-Safe: Registered outputs prevent glitches
• Resource Efficient: Minimal state encoding (2 bits for 3 states)
• Scalable: Easy to extend for additional coin denominations

👨‍💻 Author

Ayush Verma B.Tech ECE, VIT
ayushverma.ayuv@gmail.com

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Designed with passion for digital design excellence