At0m-8

Architecture of an 8-Bit CPU

An 8-bit CPU processes data 8 bits at a time. It follows the fetch–decode–execute cycle and is composed of:

• Registers
• ALU
• Control Unit
• Memory
• Buses (data, address, control)

2. Main Components

2.1 Registers

Registers store temporary data and instructions.

Common registers in an 8-bit CPU:

• Accumulator (A)
  • 8-bit register
  • Stores operands and ALU results
• Program Counter (PC)
  • Holds address of next instruction
  • Width depends on memory size (e.g., 8-bit PC → 256 memory locations)
• Instruction Register (IR)
  • Stores current instruction
  • Opcode + operand fields
• General Purpose Registers (optional)
  • R0, R1, etc. (8-bit)
• Flag Register
  • Stores status bits:
    • Zero (Z)
    • Carry (C)
    • Negative (N)

2.2 Arithmetic Logic Unit (ALU)

Performs arithmetic and logical operations.

Operations:

• ADD
• SUB
• AND
• OR
• NOT
• XOR
• INC / DEC

Inputs:

• Operand A (from Accumulator or register)
• Operand B (from register or memory)

Outputs:

• Result (8-bit)
• Flags (Carry, Zero, etc.)

2.3 Control Unit (CU)

Controls the operation of all CPU components.

Functions:

• Decodes instruction opcode

• Generates control signals

• Controls:

  • Register load/enable
  • ALU operation selection
  • Memory read/write

Types:

• Hardwired Control Unit (used in Logisim)
• Microprogrammed (advanced)

2.4 Memory Unit

Stores:

• Program instructions
• Data

Types:

• RAM (read/write)
• ROM (program storage)

Key signals:

• Address bus
• Data bus
• Read / Write control

3. Bus Structure

3.1 Data Bus

• 8-bit wide
• Transfers data between CPU and memory

3.2 Address Bus

• Carries memory addresses
• Width determines memory size
  • 8-bit → 256 locations

3.3 Control Bus

• Read
• Write
• Clock
• Reset

4. Instruction Format (Example)

8-bit Instruction:

[ Opcode (4 bits) | Operand / Address (4 bits) ]

Example:

0001 0010
ADD  R2

5. Instruction Cycle

5.1 Fetch

1. PC → Memory Address
2. Instruction loaded into IR
3. PC incremented

5.2 Decode

• Control Unit decodes opcode
• Determines required operation

5.3 Execute

• ALU performs operation
• Result stored
• Flags updated

6. Clock and Timing

• CPU operations synchronized by a clock
• Each instruction may take multiple clock cycles

        ┌──────────┐
        │  Memory  │
        └────┬─────┘
             │
     ┌───────▼────────┐
     │   Control Unit │
     └───────┬────────┘
             │
   ┌─────────▼─────────┐
   │        ALU        │
   └─────────┬─────────┘
             │
        ┌────▼────┐
        │Registers│
        └─────────┘

Clock

1. Purpose of the Clock

The clock is the heartbeat of the CPU.

• It synchronizes all operations
• Ensures data moves in a controlled, predictable way
• All registers update only on clock edges

Without a clock, the CPU would behave randomly.

2. What is a Clock Signal?

A clock signal is a square wave that alternates between:

• HIGH (1)
• LOW (0)

HIGH ────┐    ┌────
         └────┘
LOW

Each transition controls when components change state.

3. Clock Edge Triggering

In Ben Eater’s CPU:

• Registers are rising-edge triggered
• Data is latched only when the clock goes from 0 → 1

This prevents unwanted changes during computation.

4. Clock Modes

4.1 Manual Clock

• Allows stepping through the CPU one cycle at a time

• Useful for:

  • Debugging
  • Understanding instruction flow

Manual clock = Push button

4.2 Automatic Clock

• Runs continuously at a fixed frequency
• Used when the CPU works correctly

Automatic clock = Oscillator

A MUX (Multiplexer) is a digital switch that selects one input out of many and forwards it to a single output.

4.3 Clock Select (Manual / Auto)

• A MUX is used to select:

  • Manual clock
  • Automatic clock

Control signal decides the source.

5. Clock Halt (Enable / Disable)

The CPU needs the ability to pause execution.

• Implemented using:
  • AND gate
• If HALT = 1, clock pulses stop
• If HALT = 0, clock runs normally

Purpose:

• Debugging
• Implementing HLT instruction later

6. Clock Circuit in Logisim Evolution

Components Used:

• Clock (Oscillator)
• Button (Manual clock)
• Multiplexer (2:1)
• AND Gate
• Output pin (Clock output)

8-Bit Adder in CPU

A half adder adds two 1-bit binary numbers.

A full adder is a digital circuit that adds three 1-bit inputs (A, B, and Carry-in) and produces a Sum and a Carry-out. Full adders are chained together to make multi-bit adders; for example, eight full adders are used to form an 8-bit adder.

Full Adder is a combinational circuit that adds three inputs and produces two outputs. The first two inputs are A and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and the normal output is designated as S which is SUM.

Why XOR for the Sum

When you add two bits:

A	B	A + B (Sum)
0	0	0
0	1	1
1	0	1
1	1	0 (carry happens)

Now look at the XOR truth table:

A	B	A ⊕ B
0	0	0
0	1	1
1	0	1
1	1	0

Exactly the same as the sum column.

So:

• XOR gives the SUM
• It outputs 1 only when the inputs are different

2. Why AND for the Carry

A carry is produced only when both bits are 1:

A	B	Carry
0	0	0
0	1	0
1	0	0
1	1	1

Now look at AND:

A	B	A · B
0	0	0
0	1	0
1	0	0
1	1	1

Perfect match again.

So:

• AND gives the CARRY
• Carry happens only when both inputs are 1

Final Half Adder Equations

• Sum = A ⊕ B
• Carry = A · B

That’s why XOR and AND are used they naturally implement binary addition with the fewest gates.

Subtraction

CPUs do not build a separate subtraction circuit.

Instead, subtraction is performed using the same adder hardware by converting subtraction into addition.

Binary subtraction is done using Two’s Complement.

A − B = A + (Two’s Complement of B)

Example: 9 − 5

A = 0000 1001  (9)
B = 0000 0101  (5)

Invert B → 1111 1010
Carry-In = 1

Now add:

  0000 1001
+ 1111 1010
+         1
-----------
  0000 0100   (4)

XOR is reused cleverly:

• For addition:

  B ⊕ 0 = B

• For subtraction:

  B ⊕ 1 = ¬B

So CPUs use a SUB control signal:

Operation	SUB	Effect on B
Addition	0	B unchanged
Subtraction	1	B inverted

The same XOR gates handle both modes.

The method we are using is called Ripple Carry. Ripple carry is a method used in multi-bit binary adders where the carry output from one bit position is passed as the carry input to the next higher bit position.

While this is simple this is pretty slow in long term as gate gets more in numbers because each new operation needs previous carry output.

Carry Lookahead Adders (CLA)

A Carry Lookahead Adder (CLA) is a fast binary adder that reduces addition delay by computing carry bits in advance, instead of waiting for them to ripple from one bit to the next.

In a ripple-carry adder, each bit must wait for the previous carry:

FA0 → FA1 → FA2 → FA3 → ...

This makes addition slow for large bit-widths.

Carry Lookahead Adders solve this by calculating all carry signals in parallel.

For 1 bit, a Carry Lookahead Adder is just a full adder, but we name the signals clearly.

Inputs:

• A (1 bit)
• B (1 bit)
• Cin (carry in)

Outputs

• Sum
• Cout

Step 1: Generate (G)

G = A AND B

Meaning:

• This bit creates a carry by itself
• Happens only when A = 1 and B = 1

Step 2: Propagate (P)

P = A XOR B

Meaning:

• If a carry comes in, this bit will pass it forward

Step 3: Carry Lookahead Formula (No Waiting)

Cout = G OR (P AND Cin)

Meaning:

• Carry out is 1 if:

  • this bit generated a carry, OR
  • this bit passed the incoming carry

Step 4: Sum

Sum = P XOR Cin

That’s it.