🧾 Verilog Code Practice (Vivado)

Welcome to my Verilog practice repository!
This space is dedicated to building, testing, and improving digital logic designs using Verilog HDL in Xilinx Vivado.

Each project in this repository includes:

• ✅ Main Verilog design file
• 🧪 Testbench for functional simulation
• 📷 RTL schematic generated by Vivado
• ⏱️ Timing diagram from simulation results

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🔧 Tools Used

• Vivado Design Suite – for writing, simulating, and visualizing RTL designs
• GTKWave (optional) – for waveform inspection (if exported as VCD)
• Git & GitHub – for version control and progress tracking

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📁 Repository Structure

Each subfolder represents a self-contained Verilog project:

• Main folder
  • program.v
  • testbench.v
  • circuit_diagram.png
  • timing_diagram.png
  • README.md

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📂 What’s Included in Each Project

• *.v → Main Verilog design file
• *_Tb.v → Testbench module
• Test_bench.png → RTL schematic (Vivado-generated)
• Timing_diagram.png → Simulation waveform

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🚀 How to Simulate in Vivado

1. Create a new project in Vivado.
2. Add both the design and testbench .v files.
3. Set the testbench as the top module.
4. Run simulation to view waveform and RTL schematic.
5. Export timing diagrams and schematics as .png files (for documentation or GitHub).

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🧑‍💻 About Me

I'm Asmith Pampana, a B.Tech student in Electronics and Communication Engineering (ECE) at
Vidya Jyothi Institute of Technology.

I'm passionate about digital electronics, circuit design, and low-level hardware programming using Verilog.
This repository is part of my journey toward mastering HDL design and building a strong digital logic foundation.

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📌 Notes

All projects are built and tested entirely in Vivado, so waveform and schematic visuals follow Vivado's representation.
Feel free to fork, clone, or contribute — especially if you're also learning Verilog or preparing for digital design interviews or labs.

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📬 Feedback or Collaboration

If you're a fellow learner or enthusiast and want to:

• Suggest improvements
• Collaborate on HDL projects
• Ask a question about any circuit

Feel free to open an issue or start a discussion!

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📄 Licensed under the MIT License