A guide to exploring Yosys for logic synthesis.

A RISC V processor with memory hierarchy with separate instruction and data cache (tested on FPGA with GCC compiled code)

Notes I made on RTL design and verification. Currently has verilog, system verilog and formal verification notes

A tiny spice engine written in python

Convay's Game of Life on silicon (Skywater130 using OpenLane)

A simple function generator for square, sine (using CORDIC) and sawtooth waveforms on the basys3 board (with PMOD DAC)

Checking out the sky130 tool flow

Accelerator IP for computing transcendental functions using CORDIC algorithm

Project folders for CORDIC accelerator

An IOT universal remote controller using the ESP32 microcontroller (ESP32-WROOM32 module), with firmware developed using ESP-IDF

Deep learning projects implemented in pytorch as jupyter notebooks, mostly focused on computer vision

Repository for computer vision workshop orgnaized on 5/3/2022 for IEEE as part of inceptio

Analog design and simulation of a CMOS Schmitt trigger using synopsys custom design compiler for the analog design hackathon by IITH and VSD

RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instruction set simulator and a random instruction generator in s…

PCBs for experiment boards designed by dept of ECE, GEC Thrissur

Implementation of several common digital communication protocols, to be used in FPGAs.

Documentation of work done for PLL workshop for OSU 180nm node by VSD for VSD Open 2021

A repository for storing various beginner verification projects using cocotb

Some beginner projects using verilog HDL, along with some documentation on basic syntax

Extracting velocity from camera data in carla

Kalman filter for self driving cars using imu and gnss data, acquired from the carla simulator

Implementation and examples of various soft computing techniques like evolutionary algorithms and fuzzy systems