CPU-Hardwired Project

CPU design introduction

There are some types of CPU architectures out there and they can be classified according to several types of architectures:

• Von Neumann Architecture:
  The Von Neumann architecture has one memory for storing instruction and data.

• Harvard Architecture:
  The Harvard architecture has two types of memory: - instruction memory (to store instructions) - data memory (to store data that the CPU uses during program execution)

• RISC Architecture:
  RISC (Reduced Instruction Set Computer) is a CPU that implement hardware only for instruction set that in use in common compilers

• CISC Architecture:
  CISC (Complex Instruction Set Computer) has a more complex instructions in the instruction set that the compiler need to brake some instructions into sub-instructions

• Pipelined Architecture:
  The structure of the pipeline architecture is built in such a way that all instructions (in the instruction set) have a fixed number of execution stages.
  When each instruction (in the instruction set) can be decomposed into several stages, we (as CPU designers) can implement hardware that executes each step and additional hardware that chains the result of each step to the next step.
  And then when the hardware of a specific stage has finished working on an instruction it moves to execute the same stage for the next instruction.

• Single Cycle Architecture:
  The structure of this architecture is built in such a way that every instruction (in the instruction set) consume number of CPU clock cycle,
  that defined in the instruction set.
  This architecture can execute only one instruction in every clock cycle, its a significant disadvantage compare to the pipeline architecture.

Hardwired Architecture

The hardwired architecture is a Von Neumann single cycle architecture
According to the figure below, this architecture consists a bus that connected to the CPU registers and the memory.

Figure 1: Hardwired CPU Architecture

The Hardwired CPU resgisters are described in the following table:

Figure 2: Hardwired Architecture Register Description

Note: In my design TR register does not currently exist because it used for interrupt,
and I still have not implement a hardware for executing ISR (Interrupt Service Routine).

Harwired CPU Instruction Set

The instruction set of the Hardwired CPU is very basic and simple.
For each bit in the instruction has different meaning so we can easily decode the instruction into hardware to execution.

Figure 3: Hardwired CPU Instruction Set:

Design Principles

To design the CPU we need to implement in HDL (Hardware Description Language) the hardware
and verified it for check that the hardware work well as we expected.

Design Stages:

• Implementing the register modules and the memory of the CPU

• Implement the bus imterface between the modules

Note: As we can see in the architecture diagram the output of the bus connected to all the registers and the memory parallel inputs.
And also the input of the bus get the output of all of this modules.
The problem with this is when we try to connect some output signals to the same signal we got a multiple driver for this signal
and our design can be damaged.
So, we implement a multiplexer (the MuxBus module) that enable only for one input catch the bus signals.

• Implement Adder and Logic module for logic operations and arithmetic calculatations and also for transfer data between the memory and the accumulator.

• Implement the control unit module that generate the control signals.
This module does not exist in the diagram but it's a necessery module for decoding the instructions and execute them.

• Creating the top module and integrate between the sub-modules.