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1. project project Public

2. RRA RRA Public

   Designed and verified a 4-input Round-Robin Arbiter in Verilog/SystemVerilog. This project features a synchronous RTL design with a fair, rotating priority scheme to prevent resource starvation. In…

   SystemVerilog

3. Async-fifo Async-fifo Public

   This project

   Verilog

4. Filter Filter Public

   MIXER CKT

5. axi-lite-uvm-verification axi-lite-uvm-verification Public

   UVM verification environment for an AXI4-Lite slave — 4/4 tests passing, 0 errors, up to 100% functional coverage

   SystemVerilog