🏛️ Computer Architecture Lab

A comprehensive repository for digital design and computer architecture experiments 🚀

View Demo · Report Bug · Request Feature

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� Table of Contents

• 🎯 About The Project
• ✨ Features
• �️ Built With
• 🚀 Getting Started
• 📁 Repository Structure
• 🧪 Hardware Experiments
• 💻 Web Application
• 🎮 Live Demo
• 📸 Screenshots
• 🤝 Contributing
• 📜 License
• 📞 Contact

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🎯 About The Project

Welcome to the Computer Architecture Lab repository! This comprehensive project combines theoretical computer architecture concepts with practical implementations, featuring:

• Hardware Design: Complete VHDL implementations of fundamental digital circuits
• Interactive Web Platform: A modern React-based learning environment
• Educational Tools: RTL generators, waveform visualizers, and interactive labs
• Practical Experiments: From basic logic gates to complex processor architectures

This repository serves as both a learning resource and a practical toolkit for computer architecture students and enthusiasts.

✨ Features

🔧 Hardware Design Suite

• ✅ Complete VHDL implementations of logic gates
• ✅ Schematic diagrams and waveform analysis
• ✅ Testbench files for simulation
• ✅ Ready-to-use Xilinx ISE projects

🌐 Interactive Web Platform

• ✅ Modern React-based user interface
• ✅ RTL (Register Transfer Level) code generator
• ✅ Interactive waveform generator
• ✅ Virtual laboratory environment
• ✅ Educational content and tutorials

� Learning Resources

• ✅ Step-by-step experiment guides
• ✅ Visual circuit representations
• ✅ Interactive learning modules
• ✅ Comprehensive documentation

🛠️ Built With

Hardware Design

• ISE Xilinx - FPGA Design Suite
• VHDL - Hardware Description Language
• ModelSim - Simulation Environment

Web Application

• React 19 - Frontend Framework
• Vite - Build Tool & Development Server
• Framer Motion - Animation Library
• React Router - Navigation
• React Flow - Interactive Node-based UI
• React Icons - Icon Library

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🚀 Getting Started

Prerequisites

For Hardware Design:

• ISE Xilinx (Version 14.x or later)
• Windows/Linux operating system
• ModelSim (Optional, for advanced simulation)

For Web Application:

• Node.js (Version 16.x or later)
• npm or yarn package manager

Installation

1️⃣ Clone the Repository

git clone https://github.com/Anish-2005/computer-architecture-lab.git
cd computer-architecture-lab

2️⃣ Hardware Projects Setup

# Navigate to hardware assignments
cd Assignment-1

# Open any gate folder (AND Gate, OR Gate, NAND Gate)
cd "AND Gate"

# Open the .vhd files in ISE Xilinx
# Run simulations using the provided testbench files

3️⃣ Web Application Setup

# Navigate to web application
cd computer-architecture

# Install dependencies
npm install

# Start development server
npm run dev

# Build for production
npm run build

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📁 Repository Structure

Computer-Architecture-Lab/
├── 📁 Assignment-1/                 # Hardware Design Experiments
│   ├── 📁 AND Gate/
│   │   ├── 📄 andgate.vhd          # VHDL implementation
│   │   ├── 📄 andtest.vhd          # Testbench file
│   │   ├── 🖼️ schematic.png        # Circuit schematic
│   │   └── 🖼️ waveform.png         # Simulation waveform
│   ├── 📁 NAND Gate/
│   │   ├── 📄 nand-gate.vhd        # VHDL implementation
│   │   ├── 📄 nand_test.vhd        # Testbench file
│   │   ├── 🖼️ schematic.png        # Circuit schematic
│   │   └── 🖼️ waveform.png         # Simulation waveform
│   └── 📁 OR Gate/
│       ├── 📄 or_gate.vhd          # VHDL implementation
│       ├── 📄 or_test.vhd          # Testbench file
│       ├── 🖼️ schematic.png        # Circuit schematic
│       └── �️ waveform.png         # Simulation waveform
├── 📁 computer-architecture/        # Web Application
│   ├── 📁 src/
│   │   ├── 📁 pages/
│   │   │   ├── 📄 Landing.jsx      # Landing page
│   │   │   ├── 📄 Labs.jsx         # Virtual lab interface
│   │   │   ├── 📄 LearnPage.jsx    # Learning modules
│   │   │   ├── 📄 RTLGenerator.jsx # RTL code generator
│   │   │   └── 📄 WaveformGenerator.jsx # Waveform visualizer
│   │   ├── 📁 assets/              # Static assets
│   │   ├── 📄 App.jsx              # Main application
│   │   └── 📄 main.jsx             # Application entry point
│   ├── 📁 public/                  # Public assets
│   ├── 📄 package.json             # Dependencies
│   └── 📄 vite.config.js           # Vite configuration
└── 📄 README.md                    # This file

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🧪 Hardware Experiments

🔌 Assignment 1: Fundamental Logic Gates

1️⃣ AND Gate Implementation

• File: Assignment-1/AND Gate/andgate.vhd
• Features:
  • Complete VHDL implementation
  • Comprehensive testbench
  • Schematic diagram included
  • Waveform analysis

2️⃣ OR Gate Implementation

• File: Assignment-1/OR Gate/or_gate.vhd
• Features:
  • Behavioral modeling
  • Simulation testbench
  • Visual documentation

3️⃣ NAND Gate Implementation

• File: Assignment-1/NAND Gate/nand-gate.vhd
• Features:
  • Efficient VHDL code
  • Extensive testing
  • Performance analysis

🎯 How to Run Hardware Experiments

1. Open ISE Xilinx
2. Create New Project or open existing .xise file
3. Add Source Files (.vhd files from respective folders)
4. Run Behavioral Simulation using provided testbench
5. Analyze Results with included waveform images

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💻 Web Application

� Key Features

🏠 Landing Page

• Modern, responsive design
• Quick navigation to all features
• Project overview and highlights

🧪 Virtual Labs

• Interactive circuit simulation
• Real-time waveform generation
• Step-by-step experiment guidance

📚 Learn Page

• Comprehensive tutorials
• Interactive learning modules
• Progressive difficulty levels

⚡ RTL Generator

• Automated RTL code generation
• Multiple hardware description languages
• Export functionality

� Waveform Generator

• Interactive waveform creation
• Multiple signal types
• Export and analysis tools

🎮 Available Scripts

# Development
npm run dev          # Start development server

# Production
npm run build        # Build for production
npm run preview      # Preview production build

# Code Quality
npm run lint         # Run ESLint

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🎮 Live Demo

🌐 Web Application: [Coming Soon - Deploy to Vercel] 📱 Mobile Responsive: Fully optimized for all devices 🚀 Performance: Optimized with Vite for fast loading

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📸 Screenshots

🏠 Landing Page

Modern and intuitive interface

🧪 Virtual Laboratory

Interactive circuit simulation environment

📊 Waveform Generator

Real-time waveform visualization

⚡ RTL Generator

Automated code generation tool

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🤝 Contributing

We welcome contributions from the community! � Here's how you can help:

🛠️ How to Contribute

1. Fork the repository
2. Create a feature branch (git checkout -b feature/AmazingFeature)
3. Commit your changes (git commit -m 'Add some AmazingFeature')
4. Push to the branch (git push origin feature/AmazingFeature)
5. Open a Pull Request

🎯 Areas for Contribution

• 🔧 Additional hardware implementations
• 🌐 Web application enhancements
• 📚 Documentation improvements
• 🐛 Bug fixes and optimizations
• 🎨 UI/UX improvements

📋 Guidelines

• Follow existing code style
• Add comprehensive comments
• Include tests for new features
• Update documentation as needed

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📜 License

📝 This project is licensed under the MIT License - see the LICENSE file for details.

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� Contact

👨‍💻 Author

Anish Seth

• 🌐 GitHub: @Anish-2005
• 📧 Email: anishseth0510@gmail.com
• 💼 LinkedIn: Connect with me

🔗 Project Links

• 📁 Repository: Computer-Architecture-Lab
• 🐛 Issues: Report Issues
• 💡 Discussions: Join Discussions

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⭐ Star this repository if you find it helpful!

Made with ❤️ by Anish Seth

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Happy coding! 💻🚀