global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*

The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

README

@@ -1441,7 +1441,7 @@ Configuration Settings:
 		the RAM base is not zero, or RAM is divided into banks,
 		this variable needs to be recalcuated to get the address.
 
-- CONFIG_SYS_SDRAM_BASE:
+- CFG_SYS_SDRAM_BASE:
 		Physical start address of SDRAM. _Must_ be 0 here.
 
 - CONFIG_SYS_FLASH_BASE:

arch/arc/lib/cache.c

@@ -476,9 +476,9 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
 static void arc_ioc_setup(void)
 {
 	/* IOC Aperture start is equal to DDR start */
-	unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
+	unsigned int ap_base = CFG_SYS_SDRAM_BASE;
 	/* IOC Aperture size is equal to DDR size */
-	long ap_size = CONFIG_SYS_SDRAM_SIZE;
+	long ap_size = CFG_SYS_SDRAM_SIZE;
 
 	/* Unsupported configuration. See [ NOTE 2 ] for more details. */
 	if (!slc_exists())

arch/arc/lib/cpu.c

@@ -20,7 +20,7 @@ int arch_cpu_init(void)
 	timer_init();
 
 	gd->cpu_clk = get_board_sys_clk();
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	gd->ram_size = CFG_SYS_SDRAM_SIZE;
 
 	cache_init();
 

arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c

@@ -29,7 +29,7 @@
  */
 static void __secure ls1_save_ddr_head(void)
 {
-	const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
+	const char *src = (const char *)CFG_SYS_SDRAM_BASE;
 	char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
 	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
 	int i;

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -1441,7 +1441,7 @@ int dram_init_banksize(void)
 	}
 #endif
 
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
 		gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
 		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
@@ -1571,15 +1571,15 @@ void update_early_mmu_table(void)
 
 	if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
 		mmu_change_region_attr(
-					CONFIG_SYS_SDRAM_BASE,
+					CFG_SYS_SDRAM_BASE,
 					gd->ram_size,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
 					PTE_BLOCK_NS			|
 					PTE_TYPE_VALID);
 	} else {
 		mmu_change_region_attr(
-					CONFIG_SYS_SDRAM_BASE,
+					CFG_SYS_SDRAM_BASE,
 					CONFIG_SYS_DDR_BLOCK1_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|

arch/arm/dts/rockchip-optee.dtsi

@@ -32,8 +32,8 @@
 					arch = "arm";
 					os = "tee";
 					compression = "none";
-					load = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>;
-					entry = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>;
+					load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
+					entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
 
 					blob-ext {
 						filename = "tee.bin";

arch/arm/include/asm/emif.h

@@ -583,7 +583,7 @@
 	(DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\
 	(DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\
 	(DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\
-	(CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
+	(CFG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
 
 #define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL	(\
 	(DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\

arch/arm/include/asm/iproc-common/configs.h

@@ -12,6 +12,6 @@
 #define CONFIG_IPROC
 
 /* Memory Info */
-#define CONFIG_SYS_SDRAM_BASE		0x61000000
+#define CFG_SYS_SDRAM_BASE		0x61000000
 
 #endif /* __IPROC_COMMON_CONFIGS_H */

arch/arm/mach-aspeed/ast2500/board_common.c

@@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }

arch/arm/mach-aspeed/ast2600/board_common.c

@@ -54,7 +54,7 @@ int board_init(void)
 	int i = 0, rc;
 	struct udevice *dev;
 
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	while (1) {
 		rc = uclass_get_device(UCLASS_MISC, i++, &dev);

arch/arm/mach-at91/arm920t/lowlevel_init.S

@@ -114,38 +114,38 @@ SMRDATA1:
 	.word CONFIG_SYS_SDRC_CR_VAL
 	.word AT91_ASM_MC_SDRAMC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
 	.word AT91_ASM_MC_SDRAMC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL1
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
 	.word AT91_ASM_MC_SDRAMC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL2
-	.word CONFIG_SYS_SDRAM1
-	.word CONFIG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM1
+	.word CFG_SYS_SDRAM_VAL
 	.word AT91_ASM_MC_SDRAMC_TR
 	.word CONFIG_SYS_SDRC_TR_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
 	.word AT91_ASM_MC_SDRAMC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL3
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
 SMRDATA1E:
 	/* SMRDATA1 is 176 bytes long */
 #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

arch/arm/mach-at91/arm926ejs/lowlevel_init.S

@@ -201,38 +201,38 @@ SMRDATA1:
 	.word CONFIG_SYS_SDRC_MDR_VAL
 	.word AT91_ASM_SDRAMC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL2
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL1
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL1
 	.word AT91_ASM_SDRAMC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL3
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL2
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL3
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL4
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL5
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL6
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL7
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL8
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL9
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL2
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL3
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL4
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL5
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL6
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL7
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL8
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL9
 	.word AT91_ASM_SDRAMC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL4
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL10
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL10
 	.word AT91_ASM_SDRAMC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL5
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL11
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL11
 	.word AT91_ASM_SDRAMC_TR
 	.word CONFIG_SYS_SDRC_TR_VAL2
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL12
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL12
 	/* User reset enable*/
 	.word AT91_ASM_RSTC_MR
 	.word CONFIG_SYS_RSTC_RMR_VAL

arch/arm/mach-davinci/misc.c

@@ -26,14 +26,14 @@ int dram_init(void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */
 	gd->ram_size = get_ram_size(
-			(void *)CONFIG_SYS_SDRAM_BASE,
+			(void *)CFG_SYS_SDRAM_BASE,
 			CONFIG_MAX_RAM_BANK_SIZE);
 	return 0;
 }
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
 
 	return 0;

arch/arm/mach-exynos/dmc_init_ddr3.c

@@ -236,7 +236,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
  * better have similar timings, since there's only a single adjustment that is
  * shared by both chips).
  */
-const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE;
+const unsigned int test_addr = CFG_SYS_SDRAM_BASE;
 
 /* Test pattern with which RAM will be tested */
 static const unsigned int test_pattern[] = {

arch/arm/mach-imx/imx8m/soc.c

@@ -178,7 +178,7 @@ static unsigned int imx8m_find_dram_entry_in_mem_map(void)
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
-		if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
+		if (imx8m_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
 			return i;
 
 	hang();	/* Entry not found, this must never happen. */

arch/arm/mach-imx/imx8ulp/soc.c

@@ -373,7 +373,7 @@ static unsigned int imx8ulp_find_dram_entry_in_mem_map(void)
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(imx8ulp_arm64_mem_map); i++)
-		if (imx8ulp_arm64_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
+		if (imx8ulp_arm64_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
 			return i;
 
 	hang();	/* Entry not found, this must never happen. */

arch/arm/mach-imx/mx6/litesom.c

@@ -172,7 +172,7 @@ static void spl_dram_init(void)
 	 * Get actual RAM size, so we can adjust DDR row size for <512M
 	 * memories
 	 */
-	ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M);
+	ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M);
 	if (ram_size < SZ_512M) {
 		mem_ddr.rowaddr = 14;
 		mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);

arch/arm/mach-imx/mx6/opos6ul.c

@@ -44,7 +44,7 @@ static int setup_fec(void)
 int board_init(void)
 {
 	/* Address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_FEC_MXC
 	setup_fec();

arch/arm/mach-imx/spl.c

@@ -349,7 +349,7 @@ void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
 #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = imx_ddr_size();
 
 	return 0;

arch/arm/mach-k3/common.c

@@ -561,7 +561,7 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
 void spl_enable_dcache(void)
 {
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
-	phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
+	phys_addr_t ram_top = CFG_SYS_SDRAM_BASE;
 
 	dram_init();
 

arch/arm/mach-k3/r5_mpu.c

@@ -24,7 +24,7 @@ struct mpu_region_config k3_mpu_regions[16] = {
 	 O_I_WB_RD_WR_ALLOC, REGION_8MB},
 
 	/* U-Boot's code area marking it as WB and Write allocate */
-	{CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
+	{CFG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
 	 O_I_WB_RD_WR_ALLOC, REGION_2GB},
 	/* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */
 	{0x41010000, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC,

arch/arm/mach-keystone/ddr3.c

@@ -318,7 +318,7 @@ void ddr3_init_ecc(u32 base, u32 ddr3_size)
 	}
 
 	ddr3_ecc_init_range(base);
-	ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
+	ddr3_reset_data(CFG_SYS_SDRAM_BASE, ddr3_size);
 
 	/* mapping DDR3 ECC system interrupt from CIC2 to GIC */
 #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)

arch/arm/mach-mediatek/mt7623/init.c

@@ -25,7 +25,7 @@ int dram_init(void)
 {
 	u32 i;
 
-	if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) &&
+	if (((size_t)preloader_param >= CFG_SYS_SDRAM_BASE) &&
 	    ((size_t)preloader_param % sizeof(size_t) == 0) &&
 	    preloader_param->magic == BOOT_ARGUMENT_MAGIC &&
 	    preloader_param->dram_rank_num <=
@@ -35,7 +35,7 @@ int dram_init(void)
 		for (i = 0; i < preloader_param->dram_rank_num; i++)
 			gd->ram_size += preloader_param->dram_rank_size[i];
 	} else {
-		gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+		gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
 					    SZ_2G);
 	}
 

arch/arm/mach-mediatek/mt7981/init.c

@@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
 
 	return 0;
 }

arch/arm/mach-mediatek/mt7986/init.c

@@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
 
 	return 0;
 }

arch/arm/mach-mvebu/alleycat5/cpu.c

@@ -21,8 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
 static struct mm_region ac5_mem_map[] = {
 	{
 		/* RAM */
-		.phys = CONFIG_SYS_SDRAM_BASE,
-		.virt = CONFIG_SYS_SDRAM_BASE,
+		.phys = CFG_SYS_SDRAM_BASE,
+		.virt = CFG_SYS_SDRAM_BASE,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	},
@@ -102,7 +102,7 @@ int alleycat5_dram_init_banksize(void)
 	/*
 	 * Config single DRAM bank
 	 */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
 
 	return 0;