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Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig
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This converts the following to Kconfig:
   CONFIG_SYS_NAND_DBW_8
   CONFIG_SYS_NAND_DBW_16

Note that all instances of the code check for CONFIG_SYS_NAND_DBW_16
being defined, and then "else" to CONFIG_SYS_NAND_DBW_8 whereas all of
the configs set CONFIG_SYS_NAND_DBW_8. So we introduce
CONFIG_SYS_NAND_DBW_16 as an option.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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@trini
trini committed Dec 5, 2022
1 parent 1c470f3 commit 715cce6
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Showing 17 changed files with 12 additions and 16 deletions.
12 changes: 12 additions & 0 deletions drivers/mtd/nand/raw/Kconfig
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Expand Up @@ -83,6 +83,18 @@ config SPL_GENERATE_ATMEL_PMECC_HEADER
help
Generate Programmable Multibit ECC (PMECC) header for SPL image.

choice
prompt "NAND bus width (bits)"
default SYS_NAND_DBW_8

config SYS_NAND_DBW_8
bool "NAND bus width is 8 bits"

config SYS_NAND_DBW_16
bool "NAND bus width is 16 bits"

endchoice

endif

config NAND_BRCMNAND
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1 change: 0 additions & 1 deletion include/configs/at91sam9260ek.h
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Expand Up @@ -44,7 +44,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
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1 change: 0 additions & 1 deletion include/configs/at91sam9261ek.h
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Expand Up @@ -25,7 +25,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD22 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
/* our CLE is AD21 */
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1 change: 0 additions & 1 deletion include/configs/at91sam9263ek.h
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Expand Up @@ -151,7 +151,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
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1 change: 0 additions & 1 deletion include/configs/at91sam9m10g45ek.h
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Expand Up @@ -21,7 +21,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
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1 change: 0 additions & 1 deletion include/configs/at91sam9rlek.h
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Expand Up @@ -26,7 +26,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
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1 change: 0 additions & 1 deletion include/configs/at91sam9x5ek.h
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Expand Up @@ -28,7 +28,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
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1 change: 0 additions & 1 deletion include/configs/corvus.h
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Expand Up @@ -38,7 +38,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
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1 change: 0 additions & 1 deletion include/configs/ethernut5.h
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Expand Up @@ -38,7 +38,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
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1 change: 0 additions & 1 deletion include/configs/gardena-smart-gateway-at91sam.h
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Expand Up @@ -23,7 +23,6 @@

/* NAND flash */
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
/* our CLE is AD22 */
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1 change: 0 additions & 1 deletion include/configs/meesc.h
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Expand Up @@ -53,7 +53,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
# define CONFIG_SYS_NAND_DBW_8
# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
# define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
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1 change: 0 additions & 1 deletion include/configs/pm9261.h
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Expand Up @@ -130,7 +130,6 @@

/* NAND flash */
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD22 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
/* our CLE is AD21 */
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1 change: 0 additions & 1 deletion include/configs/pm9263.h
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Expand Up @@ -147,7 +147,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
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1 change: 0 additions & 1 deletion include/configs/pm9g45.h
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Expand Up @@ -26,7 +26,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
/* our CLE is AD22 */
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1 change: 0 additions & 1 deletion include/configs/smartweb.h
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Expand Up @@ -55,7 +55,6 @@

/* NAND flash settings */
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
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1 change: 0 additions & 1 deletion include/configs/snapper9g45.h
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Expand Up @@ -31,7 +31,6 @@
/* NAND Flash */
#define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
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1 change: 0 additions & 1 deletion include/configs/taurus.h
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Expand Up @@ -55,7 +55,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
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