global: Move remaining CONFIG_SYS_* to CFG_SYS_*

The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

.checkpatch.conf

@@ -4,7 +4,7 @@
 # Temporary for false positive in checkpatch
 --ignore COMPLEX_MACRO
 
-# For CONFIG_SYS_I2C_NOPROBES
+# For CFG_SYS_I2C_NOPROBES
 --ignore MULTISTATEMENT_MACRO_USE_DO_WHILE
 
 # For simple_strtoul

Kconfig

@@ -264,8 +264,8 @@ config HAS_CUSTOM_SYS_INIT_SP_ADDR
 	default y if TFABOOT
 	help
 	  Typically, we use an initial stack pointer address that is calculated
-	  by taking the statically defined CONFIG_SYS_INIT_RAM_ADDR, adding the
-	  statically defined CONFIG_SYS_INIT_RAM_SIZE and then subtracting the
+	  by taking the statically defined CFG_SYS_INIT_RAM_ADDR, adding the
+	  statically defined CFG_SYS_INIT_RAM_SIZE and then subtracting the
 	  build-time constant of GENERATED_GBL_DATA_SIZE.  On MIPS a different
 	  but statica calculation is performed.  However, some platforms will
 	  take a different approach.  Say Y here to define the address statically
@@ -333,7 +333,7 @@ config SPL_SYS_MALLOC_F_LEN
 	  particular needs this to operate, so that it can allocate the
 	  initial serial device and any others that are needed.
 
-	  It is possible to enable CONFIG_SYS_SPL_MALLOC_START to start a new
+	  It is possible to enable CFG_SYS_SPL_MALLOC_START to start a new
 	  malloc() region in SDRAM once it is inited.
 
 config TPL_SYS_MALLOC_F_LEN

Makefile

@@ -1138,10 +1138,10 @@ endif
 	$(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\
 		$(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))
 	$(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY))
-	@# CONFIG_SYS_TIMER_RATE has brackets in it for some boards which
+	@# CFG_SYS_TIMER_RATE has brackets in it for some boards which
 	@# confuses this rule. Use if() to send just a single character which
 	@# is enable to tell 'deprecated' that one of these symbols exists
-	$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CONFIG_SYS_TIMER_RATE)$(CONFIG_SYS_TIMER_COUNTER)),x))
+	$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x))
 	$(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL))
 	$(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI))
 	@# Check that this build does not use CONFIG options that we do not
@@ -1361,8 +1361,8 @@ u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE
 # U-Boot entry point, needed for booting of full-blown U-Boot
 # from the SPL U-Boot version.
 #
-ifndef CONFIG_SYS_UBOOT_START
-CONFIG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE)
+ifndef CFG_SYS_UBOOT_START
+CFG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE)
 endif
 
 # Boards with more complex image requirements can provide an .its source file
@@ -1387,18 +1387,18 @@ endif
 
 ifdef CONFIG_SPL_LOAD_FIT
 MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
 	-p $(CONFIG_FIT_EXTERNAL_OFFSET) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) \
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST)))
 else
 MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
 endif
@@ -1429,7 +1429,7 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
 UBOOT_BIN := u-boot.bin
 
 MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 
 u-boot.bin.lzma: u-boot.bin FORCE

README

@@ -341,7 +341,7 @@ The following options need to be configured:
 
 		CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
 		Physical address from the view of DDR controllers. It is the
-		same as CONFIG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
+		same as CFG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
 		it could be different for ARM SoCs.
 
 - MIPS CPU options:
@@ -352,7 +352,7 @@ The following options need to be configured:
 		be swapped if a flash programmer is used.
 
 - ARM options:
-		CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+		CFG_SYS_EXCEPTION_VECTORS_HIGH
 
 		Select high exception vectors of the ARM core, e.g., do not
 		clear the V bit of the c1 register of CP15.
@@ -415,7 +415,7 @@ The following options need to be configured:
 		the defaults discussed just above.
 
 - Cache Configuration for ARM:
-		CONFIG_SYS_PL310_BASE - Physical base address of PL310
+		CFG_SYS_PL310_BASE - Physical base address of PL310
 					controller register space
 
 - Serial Ports:
@@ -485,7 +485,7 @@ The following options need to be configured:
 - GPIO Support:
 		CONFIG_PCA953X		- use NXP's PCA953X series I2C GPIO
 
-		The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
+		The CFG_SYS_I2C_PCA953X_WIDTH option specifies a list of
 		chip-ngpio pairs that tell the PCA953X driver the number of
 		pins supported by a particular chip.
 
@@ -927,21 +927,21 @@ The following options need to be configured:
 
 		CONFIG_SYS_I2C_DIRECT_BUS
 		define this, if you don't use i2c muxes on your hardware.
-		if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
+		if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
 		omit this define.
 
-		CONFIG_SYS_I2C_MAX_HOPS
+		CFG_SYS_I2C_MAX_HOPS
 		define how many muxes are maximal consecutively connected
 		on one i2c bus. If you not use i2c muxes, omit this
 		define.
 
-		CONFIG_SYS_I2C_BUSES
+		CFG_SYS_I2C_BUSES
 		hold a list of buses you want to use, only used if
 		CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
-		a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
+		a board with CFG_SYS_I2C_MAX_HOPS = 1 and
 		CFG_SYS_NUM_I2C_BUSES = 9:
 
-		 CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP}}, \
+		 CFG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \
@@ -1044,7 +1044,7 @@ The following options need to be configured:
 		active.	 To switch to a different bus, use the 'i2c dev' command.
 		Note that bus numbering is zero-based.
 
-		CONFIG_SYS_I2C_NOPROBES
+		CFG_SYS_I2C_NOPROBES
 
 		This option specifies a list of I2C devices that will be skipped
 		when the 'i2c probe' command is issued.	 If CONFIG_I2C_MULTI_BUS
@@ -1053,16 +1053,16 @@ The following options need to be configured:
 
 		e.g.
 			#undef	CONFIG_I2C_MULTI_BUS
-			#define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
+			#define CFG_SYS_I2C_NOPROBES {0x50,0x68}
 
 		will skip addresses 0x50 and 0x68 on a board with one I2C bus
 
 			#define CONFIG_I2C_MULTI_BUS
-			#define CONFIG_SYS_I2C_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}
+			#define CFG_SYS_I2C_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}
 
 		will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
 
-		CONFIG_SYS_RTC_BUS_NUM
+		CFG_SYS_RTC_BUS_NUM
 
 		If defined, then this indicates the I2C bus number for the RTC.
 		If not defined, then U-Boot assumes that RTC is on I2C bus 0.
@@ -1120,19 +1120,19 @@ The following options need to be configured:
 		configuration if the INIT_B line goes low (which
 		indicated a CRC error).
 
-		CONFIG_SYS_FPGA_WAIT_INIT
+		CFG_SYS_FPGA_WAIT_INIT
 
 		Maximum time to wait for the INIT_B line to de-assert
 		after PROB_B has been de-asserted during a Virtex II
 		FPGA configuration sequence. The default time is 500
 		ms.
 
-		CONFIG_SYS_FPGA_WAIT_BUSY
+		CFG_SYS_FPGA_WAIT_BUSY
 
 		Maximum time to wait for BUSY to de-assert during
 		Virtex II FPGA configuration. The default is 5 ms.
 
-		CONFIG_SYS_FPGA_WAIT_CONFIG
+		CFG_SYS_FPGA_WAIT_CONFIG
 
 		Time to wait after FPGA configuration. The default is
 		200 ms.
@@ -1429,12 +1429,12 @@ Configuration Settings:
 - CONFIG_SYS_PROMPT:	This is what U-Boot prints on the console to
 		prompt for user input.
 
-- CONFIG_SYS_BAUDRATE_TABLE:
+- CFG_SYS_BAUDRATE_TABLE:
 		List of legal baudrate settings for this board.
 
-- CONFIG_SYS_MEM_RESERVE_SECURE
+- CFG_SYS_MEM_RESERVE_SECURE
 		Only implemented for ARMv8 for now.
-		If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory
+		If defined, the size of CFG_SYS_MEM_RESERVE_SECURE memory
 		is substracted from total RAM and won't be reported to OS.
 		This memory can be used as secure memory. A variable
 		gd->arch.secure_ram is used to track the location. In systems
@@ -1444,7 +1444,7 @@ Configuration Settings:
 - CFG_SYS_SDRAM_BASE:
 		Physical start address of SDRAM. _Must_ be 0 here.
 
-- CONFIG_SYS_FLASH_BASE:
+- CFG_SYS_FLASH_BASE:
 		Physical start address of Flash memory.
 
 - CONFIG_SYS_MALLOC_LEN:
@@ -1468,16 +1468,16 @@ Configuration Settings:
 		boards which do not use the full malloc in SPL (which is
 		enabled with CONFIG_SYS_SPL_MALLOC).
 
-- CONFIG_SYS_BOOTMAPSZ:
+- CFG_SYS_BOOTMAPSZ:
 		Maximum size of memory mapped by the startup code of
 		the Linux kernel; all data that must be processed by
 		the Linux kernel (bd_info, boot arguments, FDT blob if
 		used) must be put below this limit, unless "bootm_low"
 		environment variable is defined and non-zero. In such case
 		all data for the Linux kernel must be between "bootm_low"
-		and "bootm_low" + CONFIG_SYS_BOOTMAPSZ.	 The environment
+		and "bootm_low" + CFG_SYS_BOOTMAPSZ.	 The environment
 		variable "bootm_mapsize" will override the value of
-		CONFIG_SYS_BOOTMAPSZ.  If CONFIG_SYS_BOOTMAPSZ is undefined,
+		CFG_SYS_BOOTMAPSZ.  If CFG_SYS_BOOTMAPSZ is undefined,
 		then the value in "bootm_size" will be used instead.
 
 - CONFIG_SYS_BOOT_GET_CMDLINE:
@@ -1638,37 +1638,37 @@ Low Level (hardware related) configuration options:
 		Default (power-on reset) physical address of CCSR on Freescale
 		PowerPC SOCs.
 
-- CONFIG_SYS_CCSRBAR:
+- CFG_SYS_CCSRBAR:
 		Virtual address of CCSR.  On a 32-bit build, this is typically
 		the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
 
-- CONFIG_SYS_CCSRBAR_PHYS:
+- CFG_SYS_CCSRBAR_PHYS:
 		Physical address of CCSR.  CCSR can be relocated to a new
 		physical address, if desired.  In this case, this macro should
 		be set to that address.	 Otherwise, it should be set to the
 		same value as CONFIG_SYS_CCSRBAR_DEFAULT.  For example, CCSR
 		is typically relocated on 36-bit builds.  It is recommended
 		that this macro be defined via the _HIGH and _LOW macros:
 
-		#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH
-			* 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW)
+		#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH
+			* 1ull) << 32 | CFG_SYS_CCSRBAR_PHYS_LOW)
 
-- CONFIG_SYS_CCSRBAR_PHYS_HIGH:
-		Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS.	This value is typically
+- CFG_SYS_CCSRBAR_PHYS_HIGH:
+		Bits 33-36 of CFG_SYS_CCSRBAR_PHYS.	This value is typically
 		either 0 (32-bit build) or 0xF (36-bit build).	This macro is
 		used in assembly code, so it must not contain typecasts or
 		integer size suffixes (e.g. "ULL").
 
-- CONFIG_SYS_CCSRBAR_PHYS_LOW:
-		Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS.  This macro is
+- CFG_SYS_CCSRBAR_PHYS_LOW:
+		Lower 32-bits of CFG_SYS_CCSRBAR_PHYS.  This macro is
 		used in assembly code, so it must not contain typecasts or
 		integer size suffixes (e.g. "ULL").
 
 - CONFIG_SYS_IMMR:	Physical address of the Internal Memory.
 		DO NOT CHANGE unless you know exactly what you're
 		doing! (11-4) [MPC8xx systems only]
 
-- CONFIG_SYS_INIT_RAM_ADDR:
+- CFG_SYS_INIT_RAM_ADDR:
 
 		Start address of memory area that can be used for
 		initial data and stack; please note that this must be
@@ -2737,7 +2737,7 @@ locked as (mis-) used as memory, etc.
 	cause you grief during the initial boot! It is frequently not
 	used.
 
-	CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
+	CFG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
 	with your processor/board/system design. The default value
 	you will find in any recent u-boot distribution in
 	walnut.h should work for you. I'd set it to a value larger

arch/arm/cpu/arm1176/start.S

@@ -18,7 +18,7 @@
 #include <linux/linkage.h>
 
 #ifndef CONFIG_SYS_PHY_UBOOT_BASE
-#define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
+#define CONFIG_SYS_PHY_UBOOT_BASE	CFG_SYS_UBOOT_BASE
 #endif
 
 /*

arch/arm/cpu/arm926ejs/start.S

@@ -95,7 +95,7 @@ flush_dcache:
 	mrc	p15, 0, r0, c1, c0, 0
 	bic	r0, r0, #0x00000300	/* clear bits 9:8 (---- --RS) */
 	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
-#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#ifdef CFG_SYS_EXCEPTION_VECTORS_HIGH
 	orr	r0, r0, #0x00002000	/* set bit 13 (--V- ----) */
 #else
 	bic	r0, r0, #0x00002000	/* clear bit 13 (--V- ----) */

arch/arm/cpu/armv7/arch_timer.c

@@ -14,7 +14,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_SYS_HZ_CLOCK
+#ifndef CFG_SYS_HZ_CLOCK
 static inline u32 read_cntfrq(void)
 {
 	u32 frq;
@@ -29,8 +29,8 @@ int timer_init(void)
 	gd->arch.tbl = 0;
 	gd->arch.tbu = 0;
 
-#ifdef CONFIG_SYS_HZ_CLOCK
-	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
+#ifdef CFG_SYS_HZ_CLOCK
+	gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
 #else
 	gd->arch.timer_rate_hz = read_cntfrq();
 #endif

arch/arm/cpu/armv7/ls102xa/cpu.c

@@ -313,9 +313,9 @@ int cpu_eth_init(struct bd_info *bis)
 
 int arch_cpu_init(void)
 {
-	void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+	void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *rcpm2_base =
-		(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+		(void *)(CFG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
 	struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
 	u32 state;
 

arch/arm/cpu/armv7/ls102xa/fdt.c

@@ -183,7 +183,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 	off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
-					    CONFIG_SYS_IFC_ADDR);
+					    CFG_SYS_IFC_ADDR);
 	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
 #else
 	off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,

arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c

@@ -42,7 +42,7 @@ static void __secure ls1_save_ddr_head(void)
 
 static void __secure ls1_fsm_setup(void)
 {
-	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+	void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
 
 	out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
@@ -118,7 +118,7 @@ static void __secure ls1_delay(unsigned int loop)
 
 static void __secure ls1_start_fsm(void)
 {
-	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+	void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
 	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
 	struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;

arch/arm/cpu/armv7/stv0991/timer.c

@@ -18,7 +18,7 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
 				(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
 
 #define READ_TIMER()	(readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
-#define GPT_RESOLUTION	(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
+#define GPT_RESOLUTION	(CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -67,7 +67,7 @@ void __udelay(unsigned long usec)
 {
 	ulong tmo;
 	ulong start = get_timer_masked();
-	ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
+	ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100);
 	ulong rndoff;
 
 	rndoff = (usec % 10) ? 1 : 0;