armv8: lx2162a: Add Soc changes to support LX2162A

LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Android-Boot-Manager · Dec 10, 2020 · 3a187cf · 3a187cf
1 parent 2a29a9a
commit 3a187cf
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Showing 21 changed files with 171 additions and 42 deletions.
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
@@ -115,7 +115,7 @@ config PSCI_RESET
 		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
 		   !TARGET_LS1046AFRWY && \
 		   !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
-		   !TARGET_LX2160AQDS && \
+		   !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
 		   !ARCH_UNIPHIER && !TARGET_S32V234EVB
 	help
 	  Most armv8 systems have PSCI support enabled in EL3, either through

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -208,6 +208,35 @@ config ARCH_LS2080A
 	imply DISTRO_DEFAULTS
 	imply PANIC_HANG
 
+config ARCH_LX2162A
+	bool
+	select ARMV8_SET_SMPEN
+	select FSL_LSCH3
+	select NXP_LSCH3_2
+	select SYS_HAS_SERDES
+	select SYS_FSL_SRDS_1
+	select SYS_FSL_SRDS_2
+	select SYS_FSL_DDR
+	select SYS_FSL_DDR_LE
+	select SYS_FSL_DDR_VER_50
+	select SYS_FSL_EC1
+	select SYS_FSL_EC2
+	select SYS_FSL_ERRATUM_A050106
+	select SYS_FSL_HAS_RGMII
+	select SYS_FSL_HAS_SEC
+	select SYS_FSL_HAS_CCN508
+	select SYS_FSL_HAS_DDR4
+	select SYS_FSL_SEC_COMPAT_5
+	select SYS_FSL_SEC_LE
+	select ARCH_EARLY_INIT_R
+	select BOARD_EARLY_INIT_F
+	select SYS_I2C_MXC
+	select RESV_RAM if GIC_V3_ITS
+	imply DISTRO_DEFAULTS
+	imply PANIC_HANG
+	imply SCSI
+	imply SCSI_AHCI
+
 config ARCH_LX2160A
 	bool
 	select ARMV8_SET_SMPEN
@@ -345,7 +374,7 @@ config SYS_FSL_ERRATUM_A050106
 	help
 	  USB3.0 Receiver needs to enable fixed equalization
 	  for each of PHY instances in an SOC. This is similar
-	  to erratum A-009007, but this one is for LX2160A,
+	  to erratum A-009007, but this one is for LX2160A and LX2162A,
 	  and the register value is different.
 
 config SYS_FSL_ERRATUM_A010315
@@ -362,6 +391,7 @@ config MAX_CPUS
 	default 16 if ARCH_LS2080A
 	default 8 if ARCH_LS1088A
 	default 16 if ARCH_LX2160A
+	default 16 if ARCH_LX2162A
 	default 1
 	help
 	  Set this number to the maximum number of possible CPUs in the SoC.
@@ -491,6 +521,7 @@ config SYS_FSL_DUART_CLK_DIV
 	int "DUART clock divider"
 	default 1 if ARCH_LS1043A
 	default 4 if ARCH_LX2160A
+	default 4 if ARCH_LX2162A
 	default 2
 	help
 	  This is the divider that is used to derive DUART clock from Platform
@@ -502,6 +533,7 @@ config SYS_FSL_I2C_CLK_DIV
 	default 4 if ARCH_LS1012A
 	default 4 if ARCH_LS1028A
 	default 8 if ARCH_LX2160A
+	default 8 if ARCH_LX2162A
 	default 8 if ARCH_LS1088A
 	default 2
 	help
@@ -514,6 +546,7 @@ config SYS_FSL_IFC_CLK_DIV
 	default 4 if ARCH_LS1012A
 	default 4 if ARCH_LS1028A
 	default 8 if ARCH_LX2160A
+	default 8 if ARCH_LX2162A
 	default 8 if ARCH_LS1088A
 	default 2
 	help
@@ -560,14 +593,14 @@ config SYS_FSL_EC1
 	bool
 	help
 	  Ethernet controller 1, this is connected to
-	  MAC17 for LX2160A or to MAC3 for other SoCs
+	  MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
 	  Provides DPAA2 capabilities
 
 config SYS_FSL_EC2
 	bool
 	help
 	  Ethernet controller 2, this is connected to
-	  MAC18 for LX2160A or to MAC4 for other SoCs
+	  MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
 	  Provides DPAA2 capabilities
 
 config SYS_FSL_ERRATUM_A008336

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -27,6 +27,11 @@ obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
 obj-y += icid.o lx2160_ids.o
 endif
 
+ifneq ($(CONFIG_ARCH_LX2162A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
+obj-y += icid.o lx2160_ids.o
+endif
+
 ifneq ($(CONFIG_ARCH_LS2080A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
 obj-y += icid.o ls2088_ids.o

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -79,6 +79,9 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
 	CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
 	CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
+	CPU_TYPE_ENTRY(LX2162A, LX2162A, 16),
+	CPU_TYPE_ENTRY(LX2122A, LX2122A, 12),
+	CPU_TYPE_ENTRY(LX2082A, LX2082A, 8),
 };
 
 #define EARLY_PGTABLE_SIZE 0x5000
@@ -403,7 +406,7 @@ void cpu_name(char *name)
 	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
 		if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
 			strcpy(name, cpu_type_list[i].name);
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 			if (IS_C_PROCESSOR(svr))
 				strcat(name, "C");
 #endif
@@ -1229,7 +1232,7 @@ __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
 
 void __efi_runtime reset_cpu(ulong addr)
 {
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 	/* clear the RST_REQ_MSK and SW_RST_REQ */
 	out_le32(rstcr, 0x0);
 

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -9,6 +9,7 @@ SoC overview
 	7. LS2081A
 	8. LX2160A
 	9. LS1028A
+	10. LX2162A
 
 LS1043A
 ---------
@@ -379,3 +380,58 @@ The LS1028A SoC includes the following function and features:
   - Layerscape Trust Architecture
   - Service Processor (SP) provides pre-boot initialization and secure-boot
     capabilities
+
+LX2162A
+--------
+The QorIQ LX2162A processor is built on the Layerscape architecture
+combining sixteen ARM A72 processor cores with advanced, high-performance
+datapath acceleration and network, peripheral interfaces required for
+networking, wireless infrastructure, storage, and general-purpose embedded
+applications.
+
+LX2162A is compliant with the Layerscape Chassis Generation 3.2.
+
+The LX2162A SoC includes the following function and features:
+  Sixteen 32-bit / 64-bit ARM v8 A72 CPUs
+  Cache Coherent Interconnect Fabric (CCN508)
+  One 64-bit 2.9GT/s DDR4 SDRAM memory controllers with ECC.
+  Data path acceleration architecture (DPAA2)
+  12 Serdes lanes at up to 25 GHz
+  Ethernet interfaces
+  Support for 10G-SXGMII (aka USXGMII).
+  Support for SGMII (and 1000Base-KX)
+  Support for XFI (and 10GBase-KR)
+  Support for CAUI2 (50G) and 25G-AUI(25G).
+  Support for XLAUI (and 40GBase-KR4) for 40G.
+  Support for two RGMII parallel interfaces.
+  Energy efficient Ethernet support (802.3az)
+  IEEE 1588 support.
+  High-speed peripheral interfaces
+	One PCIe Gen 3.0 8-lane controllers supporting SR-IOV,
+	Two PCIe Gen 3.0 4-lane controllers.
+	Four serial ATA (SATA 3.0) controllers.
+	One USB 3.0 controllers with integrated PHY
+	Two Enhanced secure digital host controllers
+	Two Controller Area Network (CAN) modules
+	Flexible Serial peripheral interface (FlexSPI) controller.
+	Three Serial peripheral interface (SPI) controllers.
+	Eight I2C Controllers.
+	Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports.
+	General Purpose IO (GPIO)
+  Support for hardware virtualization and partitioning (ARM MMU-500)
+  Support for GIC (ARM GIC-500)
+  QorIQ platform Trust Architecture 3.0
+  One Secure WatchDog timer and one Non-Secure Watchdog timer.
+  ARM Generic Timer
+  Two Flextimers
+  Debug supporting run control, data acquisition, high-speed trace,
+  performance/event monitoring
+  Thermal Monitor Unit (TMU) with +/- 2C accuracy
+  Support for Voltage ID (VID) for yield improvement
+
+LX2162A SoC has 2 more similar SoC personalities
+1)LX2122A, few difference w.r.t. LX2162A:
+       a) Twelve 64-bit ARM v8 Cortex-A72 CPUs
+
+2)LX2082A, few difference w.r.t. LX2162A:
+       a) Eight 64-bit ARM v8 Cortex-A72 CPUs
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2018, 2020 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  */
 
@@ -26,7 +26,7 @@ static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
 
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 int xfi_dpmac[XFI14 + 1];
 int sgmii_dpmac[SGMII18 + 1];
 int a25gaui_dpmac[_25GE10 + 1];
@@ -159,7 +159,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
 		else {
 			serdes_prtcl_map[lane_prtcl] = 1;
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 			if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
 				wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
 						 (int)lane_prtcl);
@@ -552,7 +552,7 @@ void fsl_serdes_init(void)
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 	int i , j;
 
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 	for (i = XFI1, j = 1; i <= XFI14; i++, j++)
 		xfi_dpmac[i] = j;
 

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014-2015, Freescale Semiconductor, Inc.
- * Copyright 2019 NXP Semiconductors
+ * Copyright 2019-2020 NXP
  *
  * Derived from arch/power/cpu/mpc85xx/speed.c
  */
@@ -180,7 +180,7 @@ int get_clocks(void)
 #ifdef CONFIG_FSL_ESDHC
 #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
 	clock = sys_info.freq_cga_m2;
-#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A)
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2162A)
 	clock = sys_info.freq_systembus;
 #endif
 	gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2020 NXP
  */
 
 #include <common.h>
@@ -11,6 +11,22 @@ struct serdes_config {
 	u8 lanes[SRDS_MAX_LANES];
 };
 
+#if defined(CONFIG_ARCH_LX2162A)
+static struct serdes_config serdes1_cfg_tbl[] = {
+	/* SerDes 1 */
+	{0x01, {PCIE1, PCIE1, PCIE1, PCIE1 } },
+	{0x02, {SGMII6, SGMII5, SGMII4, SGMII3 } },
+	{0x03, {XFI6, XFI5, XFI4, XFI3 } },
+	{0x09, {SGMII6, SGMII5, SGMII4, PCIE1 } },
+	{0x0B, {SGMII6, SGMII5, PCIE1, PCIE1 } },
+	{0x0F, {_50GE2, _50GE2, _50GE1, _50GE1 } },
+	{0x10, {_25GE6, _25GE5, _50GE1, _50GE1 } },
+	{0x11, {_25GE6, _25GE5, _25GE4, _25GE3 } },
+	{0x12, {_25GE6, _25GE5, XFI4, XFI3 } },
+	{0x14, {_40GE1, _40GE1, _40GE1, _40GE1 } },
+	{}
+};
+#else
 static struct serdes_config serdes1_cfg_tbl[] = {
 	/* SerDes 1 */
 	{0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
@@ -48,6 +64,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 	{0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } },
 	{}
 };
+#endif
 
 static struct serdes_config serdes2_cfg_tbl[] = {
 	/* SerDes 2 */

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014-2015 Freescale Semiconductor
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  */
 
 #include <common.h>
@@ -186,7 +186,8 @@ static void erratum_a008997(void)
 	out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
 
 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
-	defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
+	defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) || \
+	defined(CONFIG_ARCH_LX2162A)
 
 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)	\
 	out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
@@ -222,7 +223,7 @@ static void erratum_a009007(void)
 #if defined(CONFIG_FSL_LSCH3)
 static void erratum_a050106(void)
 {
-#if defined(CONFIG_ARCH_LX2160A)
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 	void __iomem *dcsr = (void __iomem *)DCSR_BASE;
 
 	PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
@@ -392,7 +393,8 @@ void fsl_lsch3_early_init_f(void)
 #endif
 
 #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
-	defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
+	defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
+	defined(CONFIG_ARCH_LX2162A)
 	set_icids();
 #endif
 }

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2018, 2020 NXP
  * Copyright 2015, Freescale Semiconductor
  */
 
@@ -179,8 +179,8 @@
 #define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
 #define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
 
-/* LX2160A Soc Support */
-#elif defined(CONFIG_ARCH_LX2160A)
+/* LX2160A/LX2162A Soc Support */
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define TZPC_BASE				0x02200000
 #define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
 #if !defined(CONFIG_DM_I2C)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2018, 2020 NXP
  * Copyright 2014-2015, Freescale Semiconductor
  */
 
@@ -53,7 +53,7 @@
 #define CONFIG_SYS_FSL_WRIOP1_SIZE	0x100000000
 #define CONFIG_SYS_FSL_AIOP1_BASE	0x4b00000000
 #define CONFIG_SYS_FSL_AIOP1_SIZE	0x100000000
-#ifndef CONFIG_ARCH_LX2160A
+#if !defined(CONFIG_ARCH_LX2160A) || !defined(CONFIG_ARCH_LX2162)
 #define CONFIG_SYS_FSL_PEBUF_BASE	0x4c00000000
 #else
 #define CONFIG_SYS_FSL_PEBUF_BASE	0x1c00000000