Merge pull request #7 from lgxi24/dev

Update network.py, resolve unsupported attributes issues

fpgaconvnet/hls/generate/network.py

@@ -40,9 +40,28 @@ def __init__(self, name, partition_path, model_path, fpga_part="xc7z045ffg900-2"
 
         # set up parser
         print("FIXME: use HLS backend in Parser")
-        self.parser = Parser(backend="chisel", batch_size=self.partitions.partition[0].batch_size) # FIXME specify quant mode
+        self.parser = Parser(backend="chisel", batch_size=self.partitions.partition[0].batch_size) # FIXME for hls backend, resource model is missing
+        # modify network to be supported by onnx
+        model = onnx.load(model_path)
+        nodes = model.graph.node
+        for node in nodes:
+            attrs = node.attribute
+            for attr in attrs[:]:
+                if attr.name == 'weight_width': 
+                    assert attr.i == 16, "weight_width must be 16"
+                    attrs.remove(attr)
+                elif attr.name == 'data_width':
+                    assert attr.i == 16, "data_width must be 16"
+                    attrs.remove(attr)
+                elif attr.name == 'acc_width':
+                    attrs.remove(attr)
+                elif attr.name == 'block_floating_point':
+                    assert attr.s == b'false', "block_floating_point must be false"
+                    attrs.remove(attr)
+        new_model_path = model_path.replace('.onnx','_new.onnx')
+        onnx.save(model, new_model_path)
         # load network (parser onnx model)
-        self.net = self.parser.onnx_to_fpgaconvnet(model_path)
+        self.net = self.parser.onnx_to_fpgaconvnet(new_model_path)
         # load the existing partition information into the net object
         self.net = self.parser.prototxt_to_fpgaconvnet(self.net,partition_path)
 
@@ -184,4 +203,3 @@ def generate_all_partitions(self, num_jobs=1):
         for i in range(len(self.partitions_generator)):
             self.generate_partition(i)
 
-