Nova1

NOVA is a open source RISCV-based Application Class SoC. This project provided students with hands on development experience with latest technologies and focused on latest open-source tools and low-cost development methodologies. It has also been verified in AWS FPGA prototypes.

We have released both the Verilog RTL code as well as synthesis and back-end flow with complete guiding documentaation.

Objectives

• To enable students to learn industry based hard skills and experience of the use of soft skills required in a group projects.
• To provide students with hands-on implementation experience with latest technologies and environments.
• To build an application class SoC Focused on latest open-source tools and low-cost development methodologies.
  • Linux, RISCV, SystemVerilog
  • AWS Cloud FPGA, Xilinx Vivado, Verilator

Staffed by student team with industry mentors.

Documentation

There are several detailed pieces of documentation about Nova1 in the docs folder listed below:

• AWS Cloud FPGA
• AXI Lite Interface
• Booting Zephyr RTOS Kernel
• NOVA Emulation Documentation
• Nova1 Simulation Presentation
• RTL Simulation for Verilog/VHDL Custom Logic Design with AWS HDK

Block Diagram

Build Prerequisites

git clone https://github.com/The-Nova-Project/Nova1
cd Nova1
git submodule update --init --recursive

Build Instruction

To Build the CL-design, source the environment variables for Scalar-Unit and AWS-FPGA by runing the script:

cd aws-fpga
source hdk_setup.sh
source sdk_setup.sh
cd ../scalar-unit
source setup.bash

Setup the Custom Logic directory Path.

cd ../Custom_Logic/
export CL_DIR=$(pwd)

Test Simulation On Vivado.

cd verif/scripts/
make TEST=test_file

The Pre-built testbench test_ddr_peek_poke reads the ddr_to_bram.hex file which contains the test assembly.

make TEST=test_ddr_peek_poke

Expected Output

Snapshot tb.

cd ../sim/vivado/test_ddr_peek_poke_sv/
xsim -gui tb

AWS-FPGA EC2 Porting

To clear the AFI, use the following command will clear the FPGA image, including internal and external memories and expose the default AFI Vendor and Device Id, and display the final state for the given FPGA slot number. sudo fpga-clear-local-image -S 0 -H

To load the AFI, use the FPGA slot number and Amazon Global FPGA Image ID parameters; this command will wait for the AFI to transition to the "loaded" state. And expose the unique AFI Vendor and Device Id, and display the final state for the given FPGA slot number.

sudo fpga-load-local-image -S 0 -I agfi-01e33810ff4c9d23c

Expected Output

[muheet@ip-172-33-7-206 runtime]$ sudo fpga-clear-local-image -S 0 -H
Type  FpgaImageSlot  FpgaImageId             StatusName    StatusCode   ErrorName    ErrorCode   ShVersion
AFI          0       none                    cleared           1        ok               0       0x04261818
Type  FpgaImageSlot  VendorId    DeviceId    DBDF
AFIDEVICE    0       0x1d0f      0x1042      0000:00:1d.0


[muheet@ip-172-33-7-206 runtime]$ sudo fpga-load-local-image -S 0 -I agfi-01e33810ff4c9d23c

AFI          0       agfi-01e33810ff4c9d23c  loaded            0        ok               0       0x04261818
AFIDEVICE    0       0x1d0f      0xf000      0000:00:1d.0

Runtime Driver

This repo contains AWS-FPGA compatible Runtime C Drivers that will drive the AWS-FPGA CL Designs to interract with the Cloud FPGA via AFI.

How to Run

1. First Copy the Driver you want to run. (Considering the AFI is loaded in slot 0)
2. Paste it in your design's software/runtime directory.
3. Open Terminal in this directory.
4. First type make driverName (for example if the driver is loader.c then type make loader)
5. Then once the driver is compiled successfully type sudo ./driverName (for example if driver if bramLoader.c then type sudo ./loader *args)
6. All the interactions that the driver has done with the FPGA will be shown on the terminal screen

Drivers

This repo contains the following drivers

Driver	Format	Purpose
Loader	./BRAMLoader <hex-file>/<elf-file> dma/bram	Reads a hex/elf file and stores the data into BRAM/DMA (WORD aligned)
UART	./uart_recieve	Transmit and Receive data through UART via OCL Interface

Booting Zephyr RTOS

Zephyr RTOS is based on a small footprint kernel design. Every Zephyr application is based on the zephyr kernel. The configurable nature of the kernel allows only those features needed by your application making it ideal for systems with limited amounts of memory (as small as 2 KB!).

Getting Started

Welcome to Zephyr! See the Introduction to Zephyr for a high-level overview, and the documentation's Getting Started Guide to start developing.(Note make sure that you have clone zephyr from The-Nova-Project)

Build and Configuration

The configuration phase begins when the user generates a build system, specifying a board target and a source application directory.

$  cd zephyrproject/zephyr
$  west build -b aws_fpga samples/uartlte/

aws-fpga is the board target and samples/uartlite/ is the application directory. developer also create own application directory in samples/uartlite. samples/uartlite/main.c. After executing the above command build folder is generated which contains all the output files like .elf, .dis, .bin etc).

Expected Output

[99/109] Linking C executable zephyr/zephyr_pre0.elf

[103/109] Linking C executable zephyr/zephyr_pre1.elf

[109/109] Linking C executable zephyr/zephyr.elf
Memory region         Used Size  Region Size  %age Used
             RAM:        3712 B      2050 MB      0.00%
        IDT_LIST:          0 GB         2 KB      0.00%

After build the application with the zephyr kernel. We get zephyr.elf and .lst. By using objcopy extract verilog hex from .elf file.

cd build/zephyr/
riscv64-unknown-elf-objcopy -O verilog zephyr.elf hex.txt

Generated hex will be dumped on DDR-A from the shell DMA port. So we can simply fetch the data of BRAM from BAR_1 and UART data from OCL interface through the runtime driver.

Hello World Example

Once the kernel is loaded in the DDR and after the reset is disabled, Hydra start fetching the kernel from DDR due to having DDR boot address set in it. We have two peripheral UART and BRAM to check the expected output of the main application. Hydra transmit the data on UART and uart is connect with OCL interface so we access the data through UART via OCL interface using runtime driver.

• sudo ./DDRLoader
• sudo ./uart_recieve

Expected Output

[muheet@ip-172-33-7-206 runtime]$ sudo ./uart_receive 
AFI PCI  Vendor ID: 0x1d0f, Device ID 0xf000

 ----------------------------Receiving Data from Target UART---------------------------- 

Hello_world

 ------From CORE to UART1 and UART1 to UART2 transmission complete------

Debugging

NOVA supports the RISC-V External Debug Draft Spec and hence you can debug (and program) the AWS-FPGA using OpenOCD. We provide two example scripts for OpenOCD below.

To get started you require to run OpenOCD configuration file as the below command

/home/muheet/Nova1/Custom_Logic/software/runtime

In this is the case, you can go on and start openocd with the runtime/aws_f1_pcie_xvc.cfg configuration file below.

sudo /home/shared/tools/experimental/openocd_aws_f1_xvc_app_bar0/bin/openocd -f aws_f1_pcie_xvc.cfg

Then you will be able to either connect through telnet or with gdb:

riscv64-unknown-elf-gdb -ex "target extended-remote localhost:3333"