VeriMap is a tool for converting single-rail RTL netlists into a dual-rail circuits resistant to DPA attacks. Its main features are:
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Easy to integrate in a conventional EDA flow.
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Generated circuits are hazard-free and preserve DFT features incorporated at the logic synthesis stage.
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Support for two architectures: self-timed dual-rail or clocked dual-rail.
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Negative logic optimisation to reduce the size of the circuit and shorten the critical path.
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Alternating spacer protocol to resist DPA attacks by making the power consumption data-independent.