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17 changes: 11 additions & 6 deletions targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/spi_api.c
100644 → 100755
Original file line number Diff line number Diff line change
Expand Up @@ -123,16 +123,21 @@ int spi_master_write(spi_t *obj, int value)
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
char *rx_buffer, int rx_length, char write_fill) {
int total = (tx_length > rx_length) ? tx_length : rx_length;
int ret;

// Default write is done in each and every call, in future can create HAL API instead
LPSPI_SetDummyData(spi_address[obj->instance], write_fill);

LPSPI_MasterTransferBlocking(spi_address[obj->instance], &(lpspi_transfer_t){
.txData = (uint8_t *)tx_buffer,
.rxData = (uint8_t *)rx_buffer,
.dataSize = total,
.configFlags = kLPSPI_MasterPcs0 | kLPSPI_MasterPcsContinuous | kLPSPI_SlaveByteSwap,
});
do
{
ret = LPSPI_MasterTransferBlocking(spi_address[obj->instance], &(lpspi_transfer_t){
.txData = (uint8_t *)tx_buffer,
.rxData = (uint8_t *)rx_buffer,
.dataSize = total,
.configFlags = kLPSPI_MasterPcs0 | kLPSPI_MasterPcsContinuous | kLPSPI_SlaveByteSwap,
});

} while((ret == kStatus_LPSPI_Busy));

return total;
}
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -51,11 +51,13 @@ const PinMap PinMap_I2C_SCL[] = {
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{GPIO_AD_B0_12, UART_1, 2},
{GPIO_AD_B1_06, UART_3, 2},
{NC , NC , 0}
};

const PinMap PinMap_UART_RX[] = {
{GPIO_AD_B0_13, UART_1, 2},
{GPIO_AD_B1_07, UART_3, 2},
{NC , NC , 0}
};

Expand Down
22 changes: 13 additions & 9 deletions targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.c
100644 → 100755
Original file line number Diff line number Diff line change
Expand Up @@ -258,9 +258,9 @@ void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig)
masterConfig->cpha = kLPSPI_ClockPhaseFirstEdge;
masterConfig->direction = kLPSPI_MsbFirst;

masterConfig->pcsToSckDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2;
masterConfig->lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2;
masterConfig->betweenTransferDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2;
masterConfig->pcsToSckDelayInNanoSec = 80;
masterConfig->lastSckToPcsDelayInNanoSec = 60;
masterConfig->betweenTransferDelayInNanoSec = 160;

masterConfig->whichPcs = kLPSPI_Pcs0;
masterConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow;
Expand Down Expand Up @@ -871,14 +871,18 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf
{
}

if (txData)
/* To prevent rxfifo overflow, ensure transmitting and receiving are executed in parallel */
if(((NULL == rxData) || (rxRemainingByteCount - txRemainingByteCount)/bytesEachRead < fifoSize))
{
wordToSend = LPSPI_CombineWriteData(txData, bytesEachWrite, isByteSwap);
txData += bytesEachWrite;
}
if (txData)
{
wordToSend = LPSPI_CombineWriteData(txData, bytesEachWrite, isByteSwap);
txData += bytesEachWrite;
}

LPSPI_WriteData(base, wordToSend);
txRemainingByteCount -= bytesEachWrite;
LPSPI_WriteData(base, wordToSend);
txRemainingByteCount -= bytesEachWrite;
}

/*Check whether there is RX data in RX FIFO . Read out the RX data so that the RX FIFO would not overrun.*/
if (rxData)
Expand Down