Proper value for SCB_ICSR_RESERVED_BITS_MASK

Description

• Type: Bug?
• Related issue: #4927

---

Bug

Target
any Nordic NRF52 (and maybe NRF51?)

Toolchain:
GCC_ARM

mbed-os sha:
182bbd5

In #4927 it was mentioned by @pan- and @nvlsianpu that the value of SCB_ICSR_RESERVED_BITS_MASK should be something else. Likely 0x94403F03F.

I'm opening this as an issue in case it got forgotten due to being in a closed ticket.

[0xc0170]

@ARMmbed/team-nordic
[Mirrored to Jira]

[nvlsianpu]

Known issue for me - @jrobeson Thx for describing the issue.
[Mirrored to Jira]

@marcuschangarm: do you have any insights here?
[Mirrored to Jira]

[marcuschangarm]

We could change the fixed value to a collection of bit masks using the macros defined here: https://github.com/ARMmbed/mbed-os/blob/master/cmsis/TARGET_CORTEX_M/core_cm4.h#L481-L510

However, I'm not sure that code is even valid anymore. From the nrf_pwr_mgmt.c file in SDK 14.2:

void nrf_pwr_mgmt_run(void)
{
    PWR_MGMT_FPU_SLEEP_PREPARE();
    PWR_MGMT_SLEEP_LOCK_ACQUIRE();
    PWR_MGMT_CPU_USAGE_MONITOR_SECTION_ENTER();
    PWR_MGMT_DEBUG_PIN_SET();

    // Wait for an event.
#ifdef SOFTDEVICE_PRESENT
    if (nrf_sdh_is_enabled())
    {
        ret_code_t ret_code = sd_app_evt_wait();
        ASSERT((ret_code == NRF_SUCCESS) || (ret_code == NRF_ERROR_SOFTDEVICE_NOT_ENABLED));
        UNUSED_VARIABLE(ret_code);
    }
    else
#endif // SOFTDEVICE_PRESENT
    {
        // Wait for an event.
        __WFE();
        // Clear the internal event register.
        __SEV();
        __WFE();
    }

    PWR_MGMT_DEBUG_PIN_CLEAR();
    PWR_MGMT_CPU_USAGE_MONITOR_SECTION_EXIT();
    PWR_MGMT_SLEEP_LOCK_RELEASE();
}

[Mirrored to Jira]

@marcuschangarm : so what exactly do you mean by that? It seems like nobody else has raised this as an issue, so maybe it's just fine as it is? I know I don't know.
[Mirrored to Jira]

[marcuschangarm]

I don't think 5.9 (and SDK 14.2) has been out long enough for people to notice whether the power consumption is exactly as expected.

I'm waiting for some better power measurement equipment myself.
[Mirrored to Jira]

[TacoGrandeTX]

The current value of SCB_ICSR_RESERVED_BITS_MASK is not restrictive enough and will prevent the core from entering WFE if any interrupt is pending, even if it is not enabled. This can happen rather easily as one might lazily disable a low priority interrupt and not notice that the pending bit was set. This will forever prevent the core from sleeping. In fact this goes even deeper as architecturally an interrupt can go pending even if it is disabled in the NVIC.

We should just be checking against the VECTPENDING and VECTACTIVE bit fields in the Interrupt Control and State Register. When VECTPENDING is non-zero it indicates which interrupt is pending and enabled. Presumably we don't want to enter WFE in an exception handler, so we should also include VECTACTIVE in the bit mask.

[Mirrored to Jira]

[TacoGrandeTX]

As Marcus points out this is only relevant if the SoftDevice is disabled:
https://github.com/ARMmbed/mbed-os/blob/master/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/sleep.c#L53-L86

[Mirrored to Jira]

[TacoGrandeTX]

PR made: #8224
[Mirrored to Jira]