[LPC1549] Tickers stop working after 32-bit rollover

[neilt6]

Just noticed that Tickers quit firing on the LPC1549 at the 1:11:34 mark (when the 32-bit space overflows). Here's a code snippet to start the underlying μs timer at a high value and make testing easier:

us_ticker_init();
LPC_RIT->COUNTER_H = 0x00000047;

Update

This has just become a show-stopping bug on one of my projects, and needs to be fixed ASAP. I've investigated this issue, and it's stemming from the fact that the µs_ticker implementation on this target is using the 48-bit Repetitive Interrupt Timer (RIT) which is clocked at 72MHz. The 32-bit microsecond timestamps are being converted to 48-bit compare values that roll over at 0x0047FFFFFFB8, long before the RIT's 48-bit counter rolls over. The RIT has a mask register, but I don't think it's useful here since the rollover point isn't an even power of 2.

@0xc0170 Any ideas on what could be done to fix this?

[neilt6]

I just tried implementing µs_ticker using the Multi-Rate Timer (MRT) instead of the Repetitive Interrupt Timer (RIT), but the IRQ has to fire every 233ms for housekeeping since the MRT is only 24-bit and runs at 72MHz. This is generally bad for performance, and is going to blow up as soon as something disables interrupts for a critical section. So it looks like we're going to have to use an SCTimer...

[neilt6]

Here is my proposed replacement µs_ticker implementation using SCT3:

#define US_TICKER_TIMER_IRQn     SCT3_IRQn

int us_ticker_inited = 0;

void us_ticker_init(void) {
    if (us_ticker_inited)
        return;

    us_ticker_inited = 1;

    // Enable the SCT3 clock
    LPC_SYSCON->SYSAHBCLKCTRL1 |= (1 << 5);

    // Clear peripheral reset the SCT3
    LPC_SYSCON->PRESETCTRL1 |= (1 << 5);
    LPC_SYSCON->PRESETCTRL1 &= ~(1 << 5);

    // Configure SCT3 as a 1MHz 32-bit counter with no auto limiting or match reload
    char sctClkDiv = ((SystemCoreClock + 1000000 - 1) / 1000000) - 1;
    LPC_SCT3->CONFIG = (1 << 7) | (1 << 0);
    LPC_SCT3->CTRL = (sctClkDiv << 5) | (1 << 3) | (1 << 2);

    // Configure SCT3 event 0 to fire on match register 0
    LPC_SCT3->EV0_STATE = (1 << 0);
    LPC_SCT3->EV0_CTRL = (0x1 << 12);

    // Start SCT3
    LPC_SCT3->CTRL &= ~(1 << 2);

    // Set SCT3 interrupt vector
    NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
    NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
}

uint32_t us_ticker_read() {
    if (!us_ticker_inited)
        us_ticker_init();

    // Return SCT3 count value
    return LPC_SCT3->COUNT;
}

void us_ticker_set_interrupt(timestamp_t timestamp) {
    // Set SCT3 match register 0 (critical section)
    int wasMasked = __disable_irq();
    LPC_SCT3->CTRL |= (1 << 2);
    LPC_SCT3->MATCH0 = (uint32_t)timestamp;
    LPC_SCT3->CTRL &= ~(1 << 2);
    if (!wasMasked)
        __enable_irq();

    // Enable interrupt on SCT3 event 0
    LPC_SCT3->EVEN = (1 << 0);
}

void us_ticker_disable_interrupt(void) {
    // Disable interrupt on SCT3 event 0
    LPC_SCT3->EVEN = 0;
}

void us_ticker_clear_interrupt(void) {
    // Clear SCT3 event 0 interrupt flag
    LPC_SCT3->EVFLAG = (1 << 0);
}

Slightly annoying to have to use a critical section in us_ticker_set_interrupt(), but at least it works. I'm stress testing it right now.