Change the FMV rules so target_clones default versions must be explicitly stated #377
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labrinea
approved these changes
Jan 17, 2025
DanielKristofKiss
approved these changes
Jan 17, 2025
|
Seems like we're in agreement for this one. Can we move towards getting it merged this week? |
|
Can you rebase and resolve any conflicts? Then I'll merge it. |
This is needed to disambiguate cases such as:
```c++
// Translation unit 1
__attribute__ ((target_clone("dotprod, sve")))
int foo();
int foo() { return 1; }
```
```c
// Translation unit 2
__attribute__ ((target_clone("dotprod, sve")))
int foo() { return 2; }
```
Where with the previous specification two dispatchers would be created
and two defaults with different contents.
This is fixed by requiring default versions in target_clones to be
explicitly stated. This makes it bery simple to determine where the
dispatcher should be created accross translation units.
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With the current behavior the following example yields a linker error:
"multiple definition of `foo.default'"
// Translation Unit 1
__attribute__((target_clones("dotprod, sve"))) int foo(void) { return 1; }
// Translation Unit 2
int foo(void) { return 0; }
__attribute__((target_version("dotprod"))) int foo(void);
__attribute__((target_version("sve"))) int foo(void);
int bar(void) { return foo(); }
That is because foo.default is generated twice. As a user I don't find
this particularly intuitive. If I wanted the default to be generated
in TU1 I'd rather write target_clones("dotprod, sve", "default")
explicitly.
When changing the code I noticed that the RISC-V target defers the
resolver emission when encountering a target_version definition. This
seems accidental since it only makes sense for AArch64, where we only
emit a resolver once we've processed the entire TU, and only if the
default version is present. I've changed this so that RISC-V
immediately emmits the resolver. I adjusted the codegen tests since
the functions now appear in a different order.
Implements ARM-software/acle#377
labrinea
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…es. (#141808) With the current behavior the following example yields a linker error: "multiple definition of `foo.default'" // Translation Unit 1 __attribute__((target_clones("dotprod, sve"))) int foo(void) { return 1; } // Translation Unit 2 int foo(void) { return 0; } __attribute__((target_version("dotprod"))) int foo(void); __attribute__((target_version("sve"))) int foo(void); int bar(void) { return foo(); } That is because foo.default is generated twice. As a user I don't find this particularly intuitive. If I wanted the default to be generated in TU1 I'd rather write target_clones("dotprod, sve", "default") explicitly. When changing the code I noticed that the RISC-V target defers the resolver emission when encountering a target_version definition. This seems accidental since it only makes sense for AArch64, where we only emit a resolver once we've processed the entire TU, and only if the default version is present. I've changed this so that RISC-V immediately emmits the resolver. I adjusted the codegen tests since the functions now appear in a different order. Implements ARM-software/acle#377
llvm-sync bot
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Jun 2, 2025
…target_clones. (#141808)
With the current behavior the following example yields a linker error:
"multiple definition of `foo.default'"
// Translation Unit 1
__attribute__((target_clones("dotprod, sve"))) int foo(void) { return 1; }
// Translation Unit 2
int foo(void) { return 0; }
__attribute__((target_version("dotprod"))) int foo(void);
__attribute__((target_version("sve"))) int foo(void);
int bar(void) { return foo(); }
That is because foo.default is generated twice. As a user I don't find
this particularly intuitive. If I wanted the default to be generated in
TU1 I'd rather write target_clones("dotprod, sve", "default")
explicitly.
When changing the code I noticed that the RISC-V target defers the
resolver emission when encountering a target_version definition. This
seems accidental since it only makes sense for AArch64, where we only
emit a resolver once we've processed the entire TU, and only if the
default version is present. I've changed this so that RISC-V immediately
emmits the resolver. I adjusted the codegen tests since the functions
now appear in a different order.
Implements ARM-software/acle#377
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This patch requires default versions in target_clones to be explicitly stated.
This makes it simple to determine where the dispatcher should be created across translation units, and resolves cases (such as below) where we can end up making multiple dispatchers.
With the previous specification, my understanding is, the second translation unit would implicitly add a default. Then there would be two implementations of defaults, and so two dispatchers would be created.
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