MIPS: Loongson: Salvage the full count from the constant timer #20
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HWR $30 (Loongson64 constant timer) is 64 bits wide. However, vDSO uses `unsigned long' to read the timer count, which leads to frozen time (delta ~= 3s) when O32/N32 userspace programs request HRES time. For N32, using `u64' instead of `unsigned long' fixes the issue. The issue becomes trickier on O32. RDHWR never sign-extends the timer count before copying it into a GPR, as the kernel always sets Status.UX=1 even in O32 userspace. Aside from the frozen time, the "shadow" on the upper half also breaks subsequent logical/branch instructions relying on the GPR. Thankfully, Status.UX==1 also means that we have the full timer count available and can use 64-bit instructions to salvage it into a pair of GPR to comply with O32 ABI. Utilize (abuse?) this fact to salvage the full timer count in O32 vDSO. Fixes: "AOSCOS: MIPS: Loongson: Add constant timer support" Signed-off-by: Rong Zhang <i@rong.moe>
…timer" This reverts commit 1e094a6. With the full timer count salvaged, we can safely use RDHWR to read the timer count from Loongson64 constant timer in O32 vDSO. Signed-off-by: Rong Zhang <i@rong.moe>
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HWR $30 (Loongson64 constant timer) is 64 bits wide. However, vDSO uses `unsigned long' to read the timer count, which leads to frozen time (delta ~= 3s) when O32/N32 userspace programs request HRES time.
For N32, using `u64' instead of `unsigned long' fixes the issue.
The issue becomes trickier on O32. RDHWR never sign-extends the timer count before copying it into a GPR, as the kernel always sets Status.UX=1 even in O32 userspace. Aside from the frozen time, the "shadow" on the upper half also breaks subsequent logical/branch instructions relying on
the GPR.
Thankfully, Status.UX==1 also means that we have the full timer count available and can use 64-bit instructions to salvage it into a pair of GPR to comply with O32 ABI.
Utilize (abuse?) this fact to salvage the full timer count in O32 vDSO.