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RevySR wants to merge 67 commits into from
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sync: SG2042/SG2044/TH1520 v6.18.y patchset #17

RevySR wants to merge 67 commits into from

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@RevySR RevySR commented Dec 23, 2025

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SpriteOvO and others added 30 commits December 23, 2025 15:32
@SpriteOvO @RevySR
FROMLIST: rust: export BINDGEN_TARGET from a separate Makefile
29b0eeb 
A subsequent commit will add a new function `bindgen-option` to
`scripts/Kconfig.include`. The bindgen backend requires the `--target`
option for cross compiling, but variable `BINDGEN_TARGET` in
`rust/Makefile` cannot be exported to `scripts/Kconfig.include`.

Therefore, move this variable to a separate new `Makefile.rust` file and
include it from `scripts/Makefile` to make the exported variable
available for use in Kconfig. Place the include in the `need-compiler`
branch to avoid including it in irrelevant make targets.

Since the new file name is `Makefile.rust`, it matches an existing
MAINTAINERS rule `scripts/*rust*`, so no modification to the MAINTAINERS
file is needed.

Signed-off-by: Asuna Yang <SpriteOvO@gmail.com>
Link: https://lore.kernel.org/r/20251204-gcc-rust-v5-v5-1-2d4f20d86c24@gmail.com
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@SpriteOvO @RevySR
FROMLIST: rust: generate a fatal error if BINDGEN_TARGET is undefined
8f7fb73 
Generate a friendly fatal error if the target triplet is undefined for
bindgen, rather than having the compiler generate obscure error messages
during the build stage.

This piece of code is copied from `scripts/Makefile.clang`.

Before this commit, error messages might look like:

error: unknown argument: '-mno-riscv-attribute'
error: unsupported argument 'medany' to option '-mcmodel=' for target
'unknown'
error: unsupported option '-march=' for target ''
error: unsupported option '-mno-save-restore' for target ''
error: unknown target triple 'unknown'
panicked at bindgen/ir/context.rs:562:15:
libclang error; possible causes include:
- Invalid flag syntax
- Unrecognized flags
- Invalid flag arguments
- File I/O errors
- Host vs. target architecture mismatch

Acked-by: Miguel Ojeda <ojeda@kernel.org>
Signed-off-by: Asuna Yang <SpriteOvO@gmail.com>
Link: https://lore.kernel.org/r/20251204-gcc-rust-v5-v5-2-2d4f20d86c24@gmail.com
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@SpriteOvO @RevySR
FROMLIST: rust: add a Kconfig function to test for support of bindgen…
d76faed 
… options

Add a new `bindgen-backend-option` Kconfig function to test whether the
bindgen backend supports a given flag.

A subsequent commit will use this function to test for RISC-V extension
flags.

Signed-off-by: Asuna Yang <SpriteOvO@gmail.com>
Link: https://lore.kernel.org/r/20251204-gcc-rust-v5-v5-3-2d4f20d86c24@gmail.com
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@SpriteOvO @RevySR
FROMLIST: RISC-V: handle extension configs for bindgen, re-enable gcc…
3fb426e 
… + rust builds

Commit 33549fc ("RISC-V: disallow gcc + rust builds") disabled GCC
+ Rust builds for RISC-V due to differences in extension handling
compared to LLVM. This commit enables GCC + Rust builds again.

Add `bindgen-option` conditions for the availability of libclang to the
RISC-V extension Kconfig symbols that depend on the `cc-option`
function.

For Zicsr/Zifencei special handling, since LLVM/Clang always enables
these two extensions, either don't pass them to `-march`, or pass them
explicitly and Rust bindgen libclang must recognize them.

Clang does not support `-mno-riscv-attribute` flag, filter it out to
resolve error: unknown argument: '-mno-riscv-attribute'.

Define `BINDGEN_TARGET_riscv` to pass the target triplet to Rust bindgen
libclang for RISC-V to resolve error: unsupported argument 'medany' to
option '-mcmodel=' for target 'unknown'.

Update the documentation, GCC + Rust builds for RISC-V are now
maintained.

Acked-by: Miguel Ojeda <ojeda@kernel.org>
Signed-off-by: Asuna Yang <SpriteOvO@gmail.com>
Link: https://lore.kernel.org/r/20251204-gcc-rust-v5-v5-4-2d4f20d86c24@gmail.com
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
FROMLIST: drm/radeon: bypass no_64bit_msi with new msi64 parameter
0bcd40e 
Sophgo SG2042's MSI driver lacks 32-bit MSI support.
Added a msi64 parameter to skip the limitation and force 64-bit MSI.

Link: https://lore.kernel.org/r/20251220163338.3852399-1-gaohan@iscas.ac.cn
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
FROMLIST: ALSA: hda: intel: Introduce msi64 parameter to override 64-…
778bb75 
…bit MSI restriction

Sophgo SG2042 MSI driver does not support 32-bit MSI.
Introduce an 'msi64' kernel parameter to bypass NO_MSI64 for ATI/HDMI.

Link: https://lore.kernel.org/r/20251220170501.3972438-1-gaohan@iscas.ac.cn
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
UPSTREAM: lib/crypto: riscv: Add poly1305-core.S to .gitignore
9f926de 
poly1305-core.S is an auto-generated file, so it should be ignored.

Fixes: bef9c75 ("lib/crypto: riscv/poly1305: Import OpenSSL/CRYPTOGAMS implementation")
Cc: stable@vger.kernel.org
Signed-off-by: Charles Mirabile <cmirabil@redhat.com>
Link: https://lore.kernel.org/r/20251212184717.133701-1-cmirabil@redhat.com
Signed-off-by: Eric Biggers <ebiggers@kernel.org>
(cherry picked from commit 5a0b188)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
Revert "FROMLIST: drm/ttm: add pgprot handling for RISC-V"
eea0275 
This reverts commit 2fba856.
@RevySR
UPSTREAM: drm/ttm: add pgprot handling for RISC-V
1f11404 
The RISC-V Svpbmt privileged extension provides support for overriding
page memory coherency attributes, and, along with vendor extensions like
Xtheadmae, supports pgprot_{writecombine,noncached} on RISC-V.

Adapt the codepath that maps ttm_write_combined to pgprot_writecombine
and ttm_noncached to pgprot_noncached to RISC-V, to allow proper page
access attributes.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Tested-by: Han Gao <rabenda.cn@gmail.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Link: https://lore.kernel.org/r/20251020053523.731353-1-uwu@icenowy.me
(cherry picked from commit 4f9ffd2)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
Revert "FROMLIST: riscv: dts: sophgo: Enable SPI NOR node for SG2042_…
181733b 
…EVB_V2"

This reverts commit cee37bb.
@RevySR
Revert "FROMLIST: riscv: dts: sophgo: Enable SPI NOR node for SG2042_…
181f484 
…EVB_V1"

This reverts commit 5f6021f.
@RevySR
Revert "FROMLIST: riscv: dts: sophgo: Enable SPI NOR node for Pioneer…
4e77d2b 
…Box"

This reverts commit 8857c2e.
@RevySR
Revert "FROMLIST: riscv: dts: sophgo: Add SPI NOR node for SG2042"
cf9c3b8 
This reverts commit defa6ff.
@RevySR
Revert "FROMLIST: riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0"
e4aa4d5 
This reverts commit 831ecc4.
@RevySR
Revert "FROMLIST: riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X"
593ab8b 
This reverts commit 84fe19a.
@RevySR
Revert "FROMLIST: riscv: sophgo: dts: enable PCIe for PioneerBox"
6c1d0cf 
This reverts commit 32703ca.
@RevySR
Revert "FROMLIST: riscv: sophgo: dts: add PCIe controllers for SG2042"
bf25bc2 
This reverts commit 4cda6dc.
@unicornx @RevySR
UPSTREAM: riscv: sophgo: dts: add PCIe controllers for SG2042
9d162ec 
Add PCIe controller nodes in DTS for Sophgo SG2042.
Default they are disabled.

Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/b34d819cd763482e0ecbc5c5ea721f0101d1f844.1760929111.git.unicorn_wang@outlook.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
(cherry picked from commit 4e27aca)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@unicornx @RevySR
UPSTREAM: riscv: sophgo: dts: enable PCIe for PioneerBox
273f982 
Enable PCIe controllers for PioneerBox, which uses SG2042 SoC.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/ec474c5eefb79626dd6a4d65454da9109aaf2f4d.1760929111.git.unicorn_wang@outlook.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
(cherry picked from commit b85ad0d)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@unicornx @RevySR
UPSTREAM: riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X
885ba32 
Enable PCIe controllers for Sophgo SG2042_EVB_V1.X board,
which uses SG2042 SoC.

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/1ad96631cc9d9d7403a2bed5585d856fa101a2ef.1760929111.git.unicorn_wang@outlook.com
Tested-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
(cherry picked from commit c6c2150)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@unicornx @RevySR
UPSTREAM: riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0
45b3c38 
Enable PCIe controllers for Sophgo SG2042_EVB_V2.0 board,
which uses SG2042 SoC.

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/50a753f9b8cbd5a90b5b2df737f87fc77a9b33a7.1760929111.git.unicorn_wang@outlook.com
Tested-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
(cherry picked from commit 579d652)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@sycamoremoon @RevySR
UPSTREAM: riscv: dts: sophgo: Add SPI NOR node for SG2042
dec247a 
Add SPI NOR controller node for SG2042

Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Tested-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
Link: https://lore.kernel.org/r/20250916-sfg-spidts-v2-1-b5d9024fe1c8@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
(cherry picked from commit 59dc89f)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@sycamoremoon @RevySR
UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for PioneerBox
e3d861c 
Enable SPI NOR node for PioneerBox device tree

According to PioneerBox schematic, SPI-NOR Flash cannot support QSPI
due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1.

Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Tested-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
Link: https://lore.kernel.org/r/20250916-sfg-spidts-v2-2-b5d9024fe1c8@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
(cherry picked from commit f49314c)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@sycamoremoon @RevySR
UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1
21c359e 
Enable SPI NOR node for SG2042_EVB_V1 device tree

According to SG2042_EVB_V1 schematic, SPI-NOR Flash cannot support QSPI
due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1.

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
Link: https://lore.kernel.org/r/20250916-sfg-spidts-v2-3-b5d9024fe1c8@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
(cherry picked from commit 11f4d84)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@sycamoremoon @RevySR
UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2
1c4b31a 
Enable SPI NOR node for SG2042_EVB_V2 device tree

According to SG2042_EVB_V2 schematic, SPI-NOR Flash cannot support QSPI
due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1.

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
Link: https://lore.kernel.org/r/20250916-sfg-spidts-v2-4-b5d9024fe1c8@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
(cherry picked from commit af5eb17)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@inochisa @RevySR
UPSTREAM: dt-bindings: net: sophgo,sg2044-dwmac: add phy mode restric…
b128920 
…tion

As the ethernet controller of SG2044 and SG2042 only supports
RGMII phy. Add phy-mode property to restrict the value.

Also, since SG2042 has internal rx delay in its mac, make
only "rgmii-txid" and "rgmii-id" valid for phy-mode.

Fixes: e281c48 ("dt-bindings: net: sophgo,sg2044-dwmac: Add support for Sophgo SG2042 dwmac")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251114003805.494387-2-inochiama@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
(cherry picked from commit 6b1aa3c)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@inochisa @RevySR
UPSTREAM: net: phy: Add helper for fixing RGMII PHY mode based on int…
a8d1f95 
…ernal mac delay

The "phy-mode" property of devicetree indicates whether the PCB has
delay now, which means the mac needs to modify the PHY mode based
on whether there is an internal delay in the mac.

This modification is similar for many ethernet drivers. To simplify
code, define the helper phy_fix_phy_mode_for_mac_delays(speed, mac_txid,
mac_rxid) to fix PHY mode based on whether mac adds internal delay.

Suggested-by: Russell King (Oracle) <linux@armlinux.org.uk>
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20251114003805.494387-3-inochiama@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
(cherry picked from commit 24afd78)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@inochisa @RevySR
UPSTREAM: net: stmmac: dwmac-sophgo: Add phy interface filter
19d2a3e 
As the SG2042 has an internal rx delay, the delay should be removed
when initializing the mac, otherwise the phy will be misconfigurated.

Fixes: 543009e ("net: stmmac: dwmac-sophgo: Add support for Sophgo SG2042 SoC")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Tested-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20251114003805.494387-4-inochiama@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
(cherry picked from commit db37c6e)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
Revert "FROMLIST: perf vendor events riscv: add T-HEAD C920V2 JSON su…
24c3eb0 
…pport"

This reverts commit 472d9c0.
@inochisa @RevySR
UPSTREAM: perf vendor events riscv: add T-HEAD C920V2 JSON support
acd959d 
T-HEAD C920 has a V2 iteration, which supports Sscompmf. The V2
iteration supports the same perf events as V1.

Reuse T-HEAD c900-legacy JSON file for T-HEAD C920V2.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Acked-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
(cherry picked from commit c957328)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Michal Wilczynski and others added 26 commits December 23, 2025 16:34
@RevySR
UPSTREAM: dt-bindings: pwm: thead: Add T-HEAD TH1520 PWM controller
6e92255 
Add the Device Tree binding documentation for the T-HEAD
TH1520 SoC PWM controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Drew Fustini <fustini@kernel.org>
Reviewed-by: Elle Rhumsaa <elle@weathered-steel.dev>
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Link: https://patch.msgid.link/20251016-rust-next-pwm-working-fan-for-sending-v16-5-a5df2405d2bd@samsung.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
(cherry picked from commit a367b64)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@ojeda @RevySR
UPSTREAM: pwm: Fix Rust formatting
48b3d30 
We do our best to keep the repository `rustfmt`-clean [1], thus run the
tool to fix the formatting issue.

A trailing empty comment [2] is added in order to preserve the wanted
style for imports (otherwise the tool will compact the first two items).

Link: https://rust-for-linux.com/contributing#submit-checklist-addendum [1]
Link: https://docs.kernel.org/rust/coding-guidelines.html#style-formatting [2]
Fixes: d8046cd ("rust: pwm: Add complete abstraction layer")
Fixes: 7b3dce8 ("rust: pwm: Add Kconfig and basic data structures")
Fixes: e03724a ("pwm: Add Rust driver for T-HEAD TH1520 SoC")
Signed-off-by: Miguel Ojeda <ojeda@kernel.org>
Link: https://patch.msgid.link/20251029182502.783392-1-ojeda@kernel.org
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
(cherry picked from commit 6fe9e91)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
UPSTREAM: pwm: th1520: Fix clippy warning for redundant struct field …
9ce7daf 
…init

Clippy warns about redundant struct field initialization when the field
name and the variable name are the same (e.g., `status: status`).

No functional change.

Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Reviewed-by: Elle Rhumsaa <elle@weathered-steel.dev>
Link: https://patch.msgid.link/20251028-pwm_fixes-v1-4-25a532d31998@samsung.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
(cherry picked from commit 26dcb42)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
UPSTREAM: pwm: th1520: Use module_pwm_platform_driver! macro
c78b866 
The `pwm_th1520` Rust driver calls C functions from the `PWM` namespace,
triggering `modpost` warnings due to missing namespace import
declarations in its `.modinfo` section.

Fix these warnings and simplify the module declaration by switching from
the generic `kernel::module_platform_driver!` macro to the newly
introduced PWM-specific `kernel::module_pwm_platform_driver!` macro.
The new macro automatically handles the required `imports_ns: ["PWM"]`
declaration.

Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Reviewed-by: Troy Mitchell <troy.mitchell@linux.dev>
Reviewed-by: Elle Rhumsaa <elle@weathered-steel.dev>
Link: https://patch.msgid.link/20251028-pwm_fixes-v1-3-25a532d31998@samsung.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
(cherry picked from commit 9075cee)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@dramforever @RevySR
UPSTREAM: lib/crypto: riscv/chacha: Avoid s0/fp register
1e7d6ef 
In chacha_zvkb, avoid using the s0 register, which is the frame pointer,
by reallocating KEY0 to t5. This makes stack traces available if e.g. a
crash happens in chacha_zvkb.

No frame pointer maintenance is otherwise required since this is a leaf
function.

Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
Fixes: bb54668 ("crypto: riscv - add vector crypto accelerated ChaCha20")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20251202-riscv-chacha_zvkb-fp-v2-1-7bd00098c9dc@iscas.ac.cn
Signed-off-by: Eric Biggers <ebiggers@kernel.org>
(cherry picked from commit 4316932)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
UPSTREAM: pwm: th1520: Fix missing Kconfig dependencies
a656152 
The driver fails to build on configurations lacking COMMON_CLK (missing
clk::Clk) or HAS_IOMEM (incomplete `pwm_chip` struct on UML).

Add dependencies on ARCH_THEAD and HAS_IOMEM, and add COMMON_CLK to
ensure correct compilation and platform targeting.

Reported-by: Markus Probst <markus.probst@gmail.com>
Closes: https://lore.kernel.org/all/a66b337528d700ae92d7940a04c59206e06a8495.camel@posteo.de/
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202512020957.PqnHfe7C-lkp@intel.com/
Fixes: e03724a ("pwm: Add Rust driver for T-HEAD TH1520 SoC")
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Link: https://patch.msgid.link/20251209-fix_deps_pwm-v1-1-f7ed8bd1bd3d@samsung.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
(cherry picked from commit 3c18000)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
Revert "XUANTIE: riscv: dts: thead: Add TH1520 USB nodes"
54658f9 
This reverts commit d6d5cd5.
@RevySR
Revert "XUANTIE: riscv: dts: thead: Add TH1520 I2C nodes"
8683e23 
This reverts commit cfb8f13.
@RevySR
Revert "XUANTIE: riscv: dts: thead: Add TH1520 PWM node"
c6a0bcd 
This reverts commit 25001ec.
@RevySR
Revert "FROMLIST: riscv: dts: thead: add zfh for th1520"
af6f055 
This reverts commit bc360e5.
@RevySR
Revert "FROMLIST: riscv: dts: thead: add ziccrse for th1520"
1572066 
This reverts commit aed0eb5.
@RevySR
Revert "FROMLIST: riscv: dts: thead: add xtheadvector to the th1520 d…
e2ce2d7 
…evicetree"

This reverts commit 3e33b86.
@RevySR
UPSTREAM: riscv: dts: thead: add xtheadvector to the th1520 devicetree
4d64d40 
The th1520 support xtheadvector [1] so it can be included in the
devicetree. Also include vlenb for the cpu. And set vlenb=16 [2].

This can be tested by passing the "mitigations=off" kernel parameter.

Link: https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-4-236c22791ef9@rivosinc.com/ [1]
Link: https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2]

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>
(cherry picked from commit aef6dc0)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
UPSTREAM: riscv: dts: thead: add ziccrse for th1520
e0560e2 
Existing rv64 hardware conforms to the rva20 profile.

Ziccrse is an additional extension required by the rva20 profile, so
th1520 has this extension.

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>
(cherry picked from commit bcc3b9c)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
UPSTREAM: riscv: dts: thead: add zfh for th1520
a955ac3 
th1520 support Zfh ISA extension.
It supports the same RISC-V extensions as SG2042.

commit cb074be ("riscv: dts: sophgo: add zfh for sg2042")

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>
(cherry picked from commit fac4be7)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
UPSTREAM: riscv: dts: thead: Add PWM controller node
e3e3678 
Add the Device Tree node for the T-HEAD TH1520 SoC's PWM controller.

Reviewed-by: Drew Fustini <fustini@kernel.org>
Tested-by: Drew Fustini <fustini@kernel.org>
Reviewed-by: Elle Rhumsaa <elle@weathered-steel.dev>
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Signed-off-by: Drew Fustini <fustini@kernel.org>
(cherry picked from commit b6b00b2)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
Revert "XUANTIE: riscv: dts: thead: Enable Lichee Pi 4A USB"
0c8efaf 
This reverts commit 33d8371.
@RevySR
Revert "XUANTIE: riscv: dts: thead: Add Lichee Pi 4A IO expansions"
7337b30 
This reverts commit 27dc939.
@RevySR
Revert "XUANTIE: riscv: dts: thead: Enable Lichee Pi 4A PWM fan"
c9c97f8 
This reverts commit 4f8fb3f.
@RevySR
Revert "FROMLIST: riscv: dts: thead: lichee-pi-4a: enable HDMI"
4330283 
This reverts commit 419d3c1.
@RevySR
UPSTREAM: riscv: dts: thead: Add PWM fan and thermal control
abe8d39 
Add Device Tree nodes to enable a PWM controlled fan and it's associated
thermal management for the Lichee Pi 4A board.

This enables temperature-controlled active cooling for the Lichee Pi 4A
board based on SoC temperature.

Reviewed-by: Drew Fustini <fustini@kernel.org>
Tested-by: Drew Fustini <fustini@kernel.org>
Reviewed-by: Elle Rhumsaa <elle@weathered-steel.dev>
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Signed-off-by: Drew Fustini <fustini@kernel.org>
(cherry picked from commit a9fb9c7)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@Icenowy @RevySR
FROMLIST: riscv: dts: thead: lichee-pi-4a: enable HDMI
971ece5 
Lichee Pi 4A board features a HDMI Type-A connector connected to the
HDMI TX controller of TH1520 SoC.

Add a device tree node describing the connector, connect it to the HDMI
controller, and enable everything on this display pipeline.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Link: https://lore.kernel.org/r/20251124105226.2860845-8-uwu@icenowy.me
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@xhackerustc @RevySR
XUANTIE: riscv: dts: thead: Add TH1520 USB nodes
8641cd1 
From: revyos@2bd7874

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@xhackerustc @RevySR
XUANTIE: riscv: dts: thead: Add TH1520 I2C nodes
a5aa314 
From: revyos@ef4ac92

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@esmil @RevySR
XUANTIE: riscv: dts: thead: Add Lichee Pi 4A IO expansions
89a1d1c 
From: revyos@b41720b

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@xhackerustc @RevySR
XUANTIE: riscv: dts: thead: Enable Lichee Pi 4A USB
cd9fadb 
From: revyos@9f2a969

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
[esmil: fix gpio references]
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
[ Han Gao: remove audio_i2c ]
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@MingcongBai
Copy link

MingcongBai commented Dec 23, 2025

Picked all but 0bcd40e and 778bb75 as driver-specific hacks makes for questions like "what about devices X, Y, and Z." We can't allow too many of these - in fact, one is too many for shared code paths.

Thanks.

KexyBiscuit pushed a commit that referenced this pull request Jan 12, 2026
@tyhicks @brauner
ecryptfs: Release lower parent dentry after creating dir
5c56afd 
Fix a mkdir-induced usage count imbalance that tripped a umount_check()
BUG while unmounting the lower filesystem. Commit f046fbb
("ecryptfs: use new start_creating/start_removing APIs") added a new
dget() of the lower parent dir, in ecryptfs_mkdir(), but did not dput()
the dentry before returning from that function.

The BUG output as seen while running the eCryptfs test suite:

$ ./run_tests.sh -b 131072 -c safe,destructive -f ext4 -K -t lp-926292.sh
...
Running eCryptfs filesystem tests on ext4
lp-926292
------------[ cut here ]------------
BUG: Dentry ffff8e6692d11988{i=c,n=ECRYPTFS_FNEK_ENCRYPTED.FXZuRGZL7QAFtER.JeA46DtdKqkkQx9H2Vpmv234J5CU8YSsrUwZJK4AbXbrN5WkZ348wnqstovKKxA-}  still in use (1) [unmount of ext4 loop0]
WARNING: CPU: 7 PID: 950 at fs/dcache.c:1590 umount_check+0x5e/0x80
Modules linked in: md5 libmd5 ecryptfs encrypted_keys ext4 crc16 mbcache jbd2
CPU: 7 UID: 0 PID: 950 Comm: umount Not tainted 6.18.0-rc1-00013-gf046fbb4d81d #17 PREEMPT(full)
Hardware name: Bochs Bochs, BIOS Bochs 01/01/2011
RIP: 0010:umount_check+0x5e/0x80
Code: 88 38 06 00 00 48 8b 40 28 4c 8b 08 48 8b 46 68 48 85 c0 74 04 48 8b 50 38 51 48 c7 c7 60 32 9c b5 48 89 f1 e8 43 5e ca ff 90 <0f> 0b 90 90 58 31 c0 e9 46 9d 6c 00 41 83 f8 01 75 b8 eb a3 66 66
RSP: 0018:ffffa19940c4bdd0 EFLAGS: 00010282
RAX: 0000000000000000 RBX: ffff8e6692fad4c0 RCX: 0000000000000000
RDX: 0000000000000004 RSI: ffffa19940c4bc70 RDI: 00000000ffffffff
RBP: ffffffffb4eb5930 R08: 00000000ffffdfff R09: 0000000000000001
R10: 00000000ffffdfff R11: ffffffffb5c8a9e0 R12: ffff8e6692fad4c0
R13: ffff8e6692fad4c0 R14: ffff8e6692d11a40 R15: ffff8e6692d11988
FS:  00007f6b4b491800(0000) GS:ffff8e670506e000(0000) knlGS:0000000000000000
CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 00007f6b4b5f8d40 CR3: 0000000114eb7001 CR4: 0000000000772ef0
PKRU: 55555554
Call Trace:
 <TASK>
 d_walk+0xfd/0x370
 shrink_dcache_for_umount+0x4d/0x140
 generic_shutdown_super+0x20/0x160
 kill_block_super+0x1a/0x40
 ext4_kill_sb+0x22/0x40 [ext4]
 deactivate_locked_super+0x33/0xa0
 cleanup_mnt+0xba/0x150
 task_work_run+0x5c/0xa0
 exit_to_user_mode_loop+0xac/0xb0
 do_syscall_64+0x2ab/0xfa0
 entry_SYSCALL_64_after_hwframe+0x77/0x7f
RIP: 0033:0x7f6b4b6c2a2b
Code: c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 f3 0f 1e fa 31 f6 e9 05 00 00 00 0f 1f 44 00 00 f3 0f 1e fa b8 a6 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 05 c3 0f 1f 40 00 48 8b 15 b9 83 0d 00 f7 d8
RSP: 002b:00007ffcd5b8b498 EFLAGS: 00000246 ORIG_RAX: 00000000000000a6
RAX: 0000000000000000 RBX: 000055b84af0b9e0 RCX: 00007f6b4b6c2a2b
RDX: 0000000000000000 RSI: 0000000000000000 RDI: 000055b84af0bdf0
RBP: 00007ffcd5b8b570 R08: 0000000000000000 R09: 0000000000000000
R10: 0000000000000103 R11: 0000000000000246 R12: 000055b84af0bae0
R13: 0000000000000000 R14: 000055b84af0bdf0 R15: 0000000000000000
 </TASK>
---[ end trace 0000000000000000 ]---
EXT4-fs (loop0): unmounting filesystem 00d9ea41-f61e-43d0-a449-6be03e7e8428.
EXT4-fs (loop0): sb orphan head is 12
sb_info orphan list:
  inode loop0:12 at ffff8e66950e1df0: mode 40700, nlink 0, next 0
Assertion failure in ext4_put_super() at fs/ext4/super.c:1345: 'list_empty(&sbi->s_orphan)'

Fixes: f046fbb ("ecryptfs: use new start_creating/start_removing APIs")
Signed-off-by: Tyler Hicks <code@tyhicks.com>
Link: https://patch.msgid.link/20251223194153.2818445-3-code@tyhicks.com
Reviewed-by: Amir Goldstein <amir73il@gmail.com>
Signed-off-by: Christian Brauner <brauner@kernel.org>
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