Update (2022.09.02) (openjdk#2)

27335: [C2] Make FP register allocable
27449: Codebuffer shared stubs enhancement
27464: [C2] Fix conditionally allocatable S5 to get correct ALL_REG_mask.size()
20630: [C2] adjust register pressure closer to allocable size
22010: Refactor fast_lock/unlock assembler
23531: Support monitor count
27499: LA port of JDK-8285435: Show file and line in MacroAssembler::verify_oop for AArch64 and RISC-V platforms (Port from x86)
27338: [JVMCI] Implement JVMCI for LoongArch64
27492: unify offsets of framePoint whether javaFrame of nativeFrame
27576: Revert MacroAssembler::remove_frame
26091: C1: Enable optimizations for RISC-V and LoongArch
27183: [C2] Make T4 allocatable
26733: C2: Load float immediate by vldi
27611: build failed with --disable-precompiled-headers
26284: Rectification of JNI argument shuffling
27604: Add reg class no_CR_reg
27648: Recursive locking case is not triggered in fast_lock

Author: loongson-jvm

make/autoconf/jvm-features.m4

@@ -281,6 +281,8 @@ AC_DEFUN_ONCE([JVM_FEATURES_CHECK_JVMCI],
       AC_MSG_RESULT([yes])
     elif test "x$OPENJDK_TARGET_CPU" = "xaarch64"; then
       AC_MSG_RESULT([yes])
+    elif test "x$OPENJDK_TARGET_CPU" = "xloongarch64"; then
+      AC_MSG_RESULT([yes])
     else
       AC_MSG_RESULT([no, $OPENJDK_TARGET_CPU])
       AVAILABLE=false

src/hotspot/cpu/loongarch/abstractInterpreter_loongarch.cpp

@@ -41,7 +41,7 @@ int AbstractInterpreter::size_activation(int max_stack,
   // in AbstractInterpreterGenerator::generate_method_entry.
 
   // fixed size of an interpreter frame:
-  int overhead = frame::java_frame_sender_sp_offset -
+  int overhead = frame::sender_sp_offset -
                  frame::interpreter_frame_initial_sp_offset;
   // Our locals were accounted for by the caller (or last_frame_adjust
   // on the transition) Since the callee parameters already account

src/hotspot/cpu/loongarch/assembler_loongarch.cpp

@@ -74,6 +74,32 @@ Address::Address(address loc, RelocationHolder spec) {
   _rspec = spec;
 }
 
+bool Assembler::is_vec_imm(float val) {
+  juint x = *reinterpret_cast<juint*>(&val);
+  juint masked = x & 0x7e07ffff;
+
+  return (masked == 0x3e000000 || masked == 0x40000000);
+}
+
+bool Assembler::is_vec_imm(double val) {
+  julong x = *reinterpret_cast<julong*>(&val);
+  julong masked = x & 0x7fc0ffffffffffff;
+
+  return (masked == 0x3fc0000000000000 || masked == 0x4000000000000000);
+}
+
+int Assembler::get_vec_imm(float val) {
+  juint x = *reinterpret_cast<juint*>(&val);
+
+  return simm13((0b11011 << 8) | (((x >> 24) & 0xc0) ^ 0x40) | ((x >> 19) & 0x3f));
+}
+
+int Assembler::get_vec_imm(double val) {
+  julong x = *reinterpret_cast<julong*>(&val);
+
+  return simm13((0b11100 << 8) | (((x >> 56) & 0xc0) ^ 0x40) | ((x >> 48) & 0x3f));
+}
+
 int AbstractAssembler::code_fill_byte() {
   return 0x00;                  // illegal instruction 0x00000000
 }

src/hotspot/cpu/loongarch/assembler_loongarch.hpp

@@ -1602,6 +1602,13 @@ class Assembler : public AbstractAssembler  {
     return false;
   }
 
+  // If x is a vector loadable immediate, return true else return false.
+  static bool is_vec_imm(float x);
+  static bool is_vec_imm(double x);
+  // Return the encoded value.
+  static int get_vec_imm(float x);
+  static int get_vec_imm(double x);
+
   // LoongArch lui is sign extended, so if you wan't to use imm, you have to use the follow
   static int split_low16(int x) {
     return (x & 0xffff);
@@ -1631,6 +1638,12 @@ class Assembler : public AbstractAssembler  {
     return (x & 0xfff);
   }
 
+  static inline void split_simm32(jlong si32, jint& si12, jint& si20) {
+    si12 = ((jint)(si32 & 0xfff) << 20) >> 20;
+    si32 += (si32 & 0x800) << 1;
+    si20 = si32 >> 12;
+  }
+
   static inline void split_simm38(jlong si38, jint& si18, jint& si20) {
     si18 = ((jint)(si38 & 0x3ffff) << 14) >> 14;
     si38 += (si38 & 0x20000) << 1;
@@ -1643,6 +1656,12 @@ class Assembler : public AbstractAssembler  {
     return (x << 20) >> 20;
   }
 
+  // Convert 13-bit x to a sign-extended 13-bit integer
+  static int simm13(int x) {
+    assert(x == (x & 0x1FFF), "must be 13-bit only");
+    return (x << 19) >> 19;
+  }
+
   // Convert 26-bit x to a sign-extended 26-bit integer
   static int simm26(int x) {
     assert(x == (x & 0x3FFFFFF), "must be 26-bit only");

src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp

@@ -105,6 +105,7 @@ int C1_MacroAssembler::lock_object(Register hdr, Register obj, Register disp_hdr
   bnez(hdr, slow_case);
   // done
   bind(done);
+  increment(Address(TREG, JavaThread::held_monitor_count_offset()), 1);
   return null_check_offset;
 }
 
@@ -135,6 +136,7 @@ void C1_MacroAssembler::unlock_object(Register hdr, Register obj, Register disp_
   }
   // done
   bind(done);
+  decrement(Address(TREG, JavaThread::held_monitor_count_offset()), 1);
 }
 
 // Defines obj, preserves var_size_in_bytes
@@ -304,19 +306,19 @@ void C1_MacroAssembler::verified_entry(bool breakAtEntry) {
 }
 
 void C1_MacroAssembler::load_parameter(int offset_in_words, Register reg) {
-  // rbp, + 0: link
-  //      + 1: return address
-  //      + 2: argument with offset 0
-  //      + 3: argument with offset 1
-  //      + 4: ...
+  //  FP + -2: link
+  //     + -1: return address
+  //     +  0: argument with offset 0
+  //     +  1: argument with offset 1
+  //     +  2: ...
 
-  ld_ptr(reg, Address(FP, (offset_in_words + 2) * BytesPerWord));
+  ld_ptr(reg, Address(FP, offset_in_words * BytesPerWord));
 }
 
 #ifndef PRODUCT
 void C1_MacroAssembler::verify_stack_oop(int stack_offset) {
   if (!VerifyOops) return;
-  verify_oop_addr(Address(SP, stack_offset), "oop");
+  verify_oop_addr(Address(SP, stack_offset));
 }
 
 void C1_MacroAssembler::verify_not_null_oop(Register r) {

src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp

@@ -391,7 +391,7 @@ OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler *sasm) {
     __ st_ptr(R0, Address(TREG, Thread::pending_exception_offset()));
 
     // load issuing PC (the return address for this stub) into A1
-    __ ld_ptr(exception_pc, Address(FP, 1 * BytesPerWord));
+    __ ld_ptr(exception_pc, Address(FP, frame::return_addr_offset * BytesPerWord));
 
     // make sure that the vm_results are cleared (may be unnecessary)
     __ st_ptr(R0, Address(TREG, JavaThread::vm_result_offset()));
@@ -440,7 +440,7 @@ OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler *sasm) {
   __ st_ptr(exception_pc, Address(TREG, JavaThread::exception_pc_offset()));
 
   // patch throwing pc into return address (has bci & oop map)
-  __ st_ptr(exception_pc, Address(FP, 1 * BytesPerWord));
+  __ st_ptr(exception_pc, Address(FP, frame::return_addr_offset * BytesPerWord));
 
   // compute the exception handler.
   // the exception oop and the throwing pc are read from the fields in JavaThread
@@ -455,7 +455,7 @@ OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler *sasm) {
   __ invalidate_registers(false, true, true, true, true, true);
 
   // patch the return address, this stub will directly return to the exception handler
-  __ st_ptr(A0, Address(FP, 1 * BytesPerWord));
+  __ st_ptr(A0, Address(FP, frame::return_addr_offset * BytesPerWord));
 
   switch (id) {
     case forward_exception_id:
@@ -675,9 +675,9 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
         __ enter();
         OopMap* map = save_live_registers(sasm);
         // Retrieve bci
-        __ ld_w(bci, Address(FP, 2 * BytesPerWord));
+        __ ld_w(bci, Address(FP, 0 * BytesPerWord));
         // And a pointer to the Method*
-        __ ld_d(method, Address(FP, 3 * BytesPerWord));
+        __ ld_d(method, Address(FP, 1 * BytesPerWord));
         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), bci, method);
         oop_maps = new OopMapSet();
         oop_maps->add_gc_map(call_offset, map);