Update (2022.09.01)

* 27085: 8291640: java/beans/XMLDecoder/8028054/Task.java should use the 3-arg Class.forName
* 23726: LA port of 8265245: depChecker_<cpu> don't have any functionalities
* 27130: revert c-call convention part of 27086
* 27445: LA port of 8243392: Remodel CDS/Metaspace storage reservation
* 27427: Normalized the use of loongarch in comments
* 27395: C2: Mark non-volatile floating-registers as SOE
* 27363: Implement ZSaveLiveRegisters
* 27062: 8292362: java/lang/Thread/jni/AttachCurrentThread/AttachTest.java#id1 failed on some platforms

Author: loongson-jvm

src/hotspot/cpu/loongarch/assembler_loongarch.hpp

@@ -1602,7 +1602,7 @@ class Assembler : public AbstractAssembler  {
     return false;
   }
 
-  // LOONGARCH lui is sign extended, so if you wan't to use imm, you have to use the follow
+  // LoongArch lui is sign extended, so if you wan't to use imm, you have to use the follow
   static int split_low16(int x) {
     return (x & 0xffff);
   }
@@ -1733,7 +1733,7 @@ class Assembler : public AbstractAssembler  {
   }
 
   //---<  calculate length of instruction  >---
-  // With LOONGARCH being a RISC architecture, this always is BytesPerInstWord
+  // With LoongArch being a RISC architecture, this always is BytesPerInstWord
   // instruction must start at passed address
   static unsigned int instr_len(unsigned char *instr) { return BytesPerInstWord; }
 

src/hotspot/cpu/loongarch/bytes_loongarch.hpp

@@ -33,12 +33,12 @@ class Bytes: AllStatic {
   // Returns true if the byte ordering used by Java is different from the native byte ordering
   // of the underlying machine. For example, this is true for Intel x86, but false for Solaris
   // on Sparc.
-  // we use loongarch, so return true
+  // we use LoongArch, so return true
   static inline bool is_Java_byte_ordering_different(){ return true; }
 
 
   // Efficient reading and writing of unaligned unsigned data in platform-specific byte ordering
-  // (no special code is needed since loongarch CPUs can access unaligned data)
+  // (no special code is needed since LoongArch CPUs can access unaligned data)
   static inline u2   get_native_u2(address p)         { return *(u2*)p; }
   static inline u4   get_native_u4(address p)         { return *(u4*)p; }
   static inline u8   get_native_u8(address p)         { return *(u8*)p; }
@@ -50,7 +50,7 @@ class Bytes: AllStatic {
 
   // Efficient reading and writing of unaligned unsigned data in Java
   // byte ordering (i.e. big-endian ordering). Byte-order reversal is
-  // needed since LOONGARCH64EL CPUs use little-endian format.
+  // needed since LoongArch64 CPUs use little-endian format.
   static inline u2   get_Java_u2(address p)           { return swap_u2(get_native_u2(p)); }
   static inline u4   get_Java_u4(address p)           { return swap_u4(get_native_u4(p)); }
   static inline u8   get_Java_u8(address p)           { return swap_u8(get_native_u8(p)); }

src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch.hpp

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2021, Loongson Technology. All rights reserved.
+ * Copyright (c) 2021, 2022, Loongson Technology. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -26,7 +26,7 @@
 #ifndef CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP
 #define CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP
 
-// No FPU stack on LOONGARCH
+// No FPU stack on LoongArch
 class FpuStackSim;
 
 #endif // CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP

src/hotspot/cpu/loongarch/c1_FrameMap_loongarch_64.cpp

@@ -354,7 +354,7 @@ LIR_Opr FrameMap::stack_pointer() {
 
 // JSR 292
 LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {
-  return LIR_OprFact::illegalOpr;  // Not needed on loongarch64
+  return LIR_OprFact::illegalOpr;  // Not needed on LoongArch64
 }
 
 bool FrameMap::validate_frame() {

src/hotspot/cpu/loongarch/c2_init_loongarch.cpp

@@ -27,7 +27,7 @@
 #include "opto/compile.hpp"
 #include "opto/node.hpp"
 
-// processor dependent initialization for loongarch
+// processor dependent initialization for LoongArch
 
 extern void reg_mask_init();
 

src/hotspot/cpu/loongarch/depChecker_loongarch.cpp

@@ -377,7 +377,7 @@ void frame::verify_deopt_original_pc(CompiledMethod* nm, intptr_t* unextended_sp
 // frame::adjust_unextended_sp
 #ifdef ASSERT
 void frame::adjust_unextended_sp() {
-  // On LOONGARCH, sites calling method handle intrinsics and lambda forms are treated
+  // On LoongArch, sites calling method handle intrinsics and lambda forms are treated
   // as any other call site. Therefore, no special action is needed when we are
   // returning to any of these call sites.
 

src/hotspot/cpu/loongarch/depChecker_loongarch.hpp

@@ -94,6 +94,8 @@ void ZBarrierSetAssembler::load_at(MacroAssembler* masm,
   //
   // Slow path
   //
+  __ enter();
+
   if (dst != V0) {
     __ push(V0);
   }
@@ -112,6 +114,7 @@ void ZBarrierSetAssembler::load_at(MacroAssembler* masm,
     __ move(dst, V0);
     __ pop(V0);
   }
+  __ leave();
 
   __ bind(done);
 }
@@ -319,6 +322,57 @@ OptoReg::Name ZBarrierSetAssembler::refine_register(const Node* node, OptoReg::N
 #undef __
 #define __ _masm->
 
+class ZSaveLiveRegisters {
+private:
+  MacroAssembler* const _masm;
+  RegSet                _gp_regs;
+  FloatRegSet           _fp_regs;
+
+public:
+  void initialize(ZLoadBarrierStubC2* stub) {
+    // Record registers that needs to be saved/restored
+    RegMaskIterator rmi(stub->live());
+    while (rmi.has_next()) {
+      const OptoReg::Name opto_reg = rmi.next();
+      if (OptoReg::is_reg(opto_reg)) {
+        const VMReg vm_reg = OptoReg::as_VMReg(opto_reg);
+        if (vm_reg->is_Register()) {
+          _gp_regs += RegSet::of(vm_reg->as_Register());
+        } else if (vm_reg->is_FloatRegister()) {
+          _fp_regs += FloatRegSet::of(vm_reg->as_FloatRegister());
+        } else {
+          fatal("Unknown register type");
+        }
+      }
+    }
+
+    // Remove C-ABI SOE registers, scratch regs and _ref register that will be updated
+    _gp_regs -= RegSet::range(r23, r30) + RegSet::of(r3, r16, r19, stub->ref());
+  }
+
+  ZSaveLiveRegisters(MacroAssembler* masm, ZLoadBarrierStubC2* stub) :
+      _masm(masm),
+      _gp_regs(),
+      _fp_regs() {
+
+    // Figure out what registers to save/restore
+    initialize(stub);
+
+    // Save registers
+    __ push(_gp_regs);
+    __ push_fpu(_fp_regs);
+  }
+
+  ~ZSaveLiveRegisters() {
+    // Restore registers
+    __ pop_fpu(_fp_regs);
+    __ pop(_gp_regs);
+  }
+};
+
+#undef __
+#define __ _masm->
+
 class ZSetupArguments {
 private:
   MacroAssembler* const _masm;
@@ -363,6 +417,13 @@ class ZSetupArguments {
       }
     }
   }
+
+  ~ZSetupArguments() {
+    // Transfer result
+    if (_ref != V0) {
+      __ move(_ref, V0);
+    }
+  }
 };
 
 #undef __
@@ -374,23 +435,10 @@ void ZBarrierSetAssembler::generate_c2_load_barrier_stub(MacroAssembler* masm, Z
   // Stub entry
   __ bind(*stub->entry());
 
-  Register ref = stub->ref();
-
   {
-    if (ref != V0) {
-      __ push(V0);
-    }
-    __ pushad_except_v0();
-
+    ZSaveLiveRegisters save_live_registers(masm, stub);
     ZSetupArguments setup_arguments(masm, stub);
     __ call_VM_leaf(stub->slow_path(), 2);
-
-    __ popad_except_v0();
-
-    if (ref != V0) {
-      __ move(ref, V0);
-      __ pop(V0);
-    }
   }
   // Stub exit
   __ b(*stub->continuation());

src/hotspot/cpu/loongarch/frame_loongarch.cpp

@@ -25,7 +25,7 @@
 
 #ifndef CPU_LOONGARCH_GLOBALDEFINITIONS_LOONGARCH_HPP
 #define CPU_LOONGARCH_GLOBALDEFINITIONS_LOONGARCH_HPP
-// Size of LOONGARCH Instructions
+// Size of LoongArch Instructions
 const int BytesPerInstWord = 4;
 
 const int StackAlignmentInBytes = (2*wordSize);
@@ -48,8 +48,6 @@ const bool CCallingConventionRequiresIntsAsLongs = false;
 
 #define SUPPORT_RESERVED_STACK_AREA
 
-#define PREFERRED_METASPACE_ALIGNMENT
-
 #define COMPRESSED_CLASS_POINTERS_DEPENDS_ON_COMPRESSED_OOPS false
 
 #define USE_POINTERS_TO_REGISTER_IMPL_ARRAY