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Update (2022.09.01)
* 27085: 8291640: java/beans/XMLDecoder/8028054/Task.java should use the 3-arg Class.forName * 23726: LA port of 8265245: depChecker_<cpu> don't have any functionalities * 27130: revert c-call convention part of 27086 * 27445: LA port of 8243392: Remodel CDS/Metaspace storage reservation * 27427: Normalized the use of loongarch in comments * 27395: C2: Mark non-volatile floating-registers as SOE * 27363: Implement ZSaveLiveRegisters * 27062: 8292362: java/lang/Thread/jni/AttachCurrentThread/AttachTest.java#id1 failed on some platforms
1 parent fee26ec commit 1093dc1

28 files changed

+170
-112
lines changed

src/hotspot/cpu/loongarch/assembler_loongarch.hpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1602,7 +1602,7 @@ class Assembler : public AbstractAssembler {
16021602
return false;
16031603
}
16041604

1605-
// LOONGARCH lui is sign extended, so if you wan't to use imm, you have to use the follow
1605+
// LoongArch lui is sign extended, so if you wan't to use imm, you have to use the follow
16061606
static int split_low16(int x) {
16071607
return (x & 0xffff);
16081608
}
@@ -1733,7 +1733,7 @@ class Assembler : public AbstractAssembler {
17331733
}
17341734

17351735
//---< calculate length of instruction >---
1736-
// With LOONGARCH being a RISC architecture, this always is BytesPerInstWord
1736+
// With LoongArch being a RISC architecture, this always is BytesPerInstWord
17371737
// instruction must start at passed address
17381738
static unsigned int instr_len(unsigned char *instr) { return BytesPerInstWord; }
17391739

src/hotspot/cpu/loongarch/bytes_loongarch.hpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -33,12 +33,12 @@ class Bytes: AllStatic {
3333
// Returns true if the byte ordering used by Java is different from the native byte ordering
3434
// of the underlying machine. For example, this is true for Intel x86, but false for Solaris
3535
// on Sparc.
36-
// we use loongarch, so return true
36+
// we use LoongArch, so return true
3737
static inline bool is_Java_byte_ordering_different(){ return true; }
3838

3939

4040
// Efficient reading and writing of unaligned unsigned data in platform-specific byte ordering
41-
// (no special code is needed since loongarch CPUs can access unaligned data)
41+
// (no special code is needed since LoongArch CPUs can access unaligned data)
4242
static inline u2 get_native_u2(address p) { return *(u2*)p; }
4343
static inline u4 get_native_u4(address p) { return *(u4*)p; }
4444
static inline u8 get_native_u8(address p) { return *(u8*)p; }
@@ -50,7 +50,7 @@ class Bytes: AllStatic {
5050

5151
// Efficient reading and writing of unaligned unsigned data in Java
5252
// byte ordering (i.e. big-endian ordering). Byte-order reversal is
53-
// needed since LOONGARCH64EL CPUs use little-endian format.
53+
// needed since LoongArch64 CPUs use little-endian format.
5454
static inline u2 get_Java_u2(address p) { return swap_u2(get_native_u2(p)); }
5555
static inline u4 get_Java_u4(address p) { return swap_u4(get_native_u4(p)); }
5656
static inline u8 get_Java_u8(address p) { return swap_u8(get_native_u8(p)); }

src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch.hpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved.
3-
* Copyright (c) 2021, Loongson Technology. All rights reserved.
3+
* Copyright (c) 2021, 2022, Loongson Technology. All rights reserved.
44
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
55
*
66
* This code is free software; you can redistribute it and/or modify it
@@ -26,7 +26,7 @@
2626
#ifndef CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP
2727
#define CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP
2828

29-
// No FPU stack on LOONGARCH
29+
// No FPU stack on LoongArch
3030
class FpuStackSim;
3131

3232
#endif // CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP

src/hotspot/cpu/loongarch/c1_FrameMap_loongarch_64.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -354,7 +354,7 @@ LIR_Opr FrameMap::stack_pointer() {
354354

355355
// JSR 292
356356
LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {
357-
return LIR_OprFact::illegalOpr; // Not needed on loongarch64
357+
return LIR_OprFact::illegalOpr; // Not needed on LoongArch64
358358
}
359359

360360
bool FrameMap::validate_frame() {

src/hotspot/cpu/loongarch/c2_init_loongarch.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@
2727
#include "opto/compile.hpp"
2828
#include "opto/node.hpp"
2929

30-
// processor dependent initialization for loongarch
30+
// processor dependent initialization for LoongArch
3131

3232
extern void reg_mask_init();
3333

src/hotspot/cpu/loongarch/depChecker_loongarch.cpp

Lines changed: 0 additions & 30 deletions
This file was deleted.

src/hotspot/cpu/loongarch/depChecker_loongarch.hpp

Lines changed: 0 additions & 31 deletions
This file was deleted.

src/hotspot/cpu/loongarch/frame_loongarch.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -377,7 +377,7 @@ void frame::verify_deopt_original_pc(CompiledMethod* nm, intptr_t* unextended_sp
377377
// frame::adjust_unextended_sp
378378
#ifdef ASSERT
379379
void frame::adjust_unextended_sp() {
380-
// On LOONGARCH, sites calling method handle intrinsics and lambda forms are treated
380+
// On LoongArch, sites calling method handle intrinsics and lambda forms are treated
381381
// as any other call site. Therefore, no special action is needed when we are
382382
// returning to any of these call sites.
383383

src/hotspot/cpu/loongarch/gc/z/zBarrierSetAssembler_loongarch.cpp

Lines changed: 62 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -94,6 +94,8 @@ void ZBarrierSetAssembler::load_at(MacroAssembler* masm,
9494
//
9595
// Slow path
9696
//
97+
__ enter();
98+
9799
if (dst != V0) {
98100
__ push(V0);
99101
}
@@ -112,6 +114,7 @@ void ZBarrierSetAssembler::load_at(MacroAssembler* masm,
112114
__ move(dst, V0);
113115
__ pop(V0);
114116
}
117+
__ leave();
115118

116119
__ bind(done);
117120
}
@@ -319,6 +322,57 @@ OptoReg::Name ZBarrierSetAssembler::refine_register(const Node* node, OptoReg::N
319322
#undef __
320323
#define __ _masm->
321324

325+
class ZSaveLiveRegisters {
326+
private:
327+
MacroAssembler* const _masm;
328+
RegSet _gp_regs;
329+
FloatRegSet _fp_regs;
330+
331+
public:
332+
void initialize(ZLoadBarrierStubC2* stub) {
333+
// Record registers that needs to be saved/restored
334+
RegMaskIterator rmi(stub->live());
335+
while (rmi.has_next()) {
336+
const OptoReg::Name opto_reg = rmi.next();
337+
if (OptoReg::is_reg(opto_reg)) {
338+
const VMReg vm_reg = OptoReg::as_VMReg(opto_reg);
339+
if (vm_reg->is_Register()) {
340+
_gp_regs += RegSet::of(vm_reg->as_Register());
341+
} else if (vm_reg->is_FloatRegister()) {
342+
_fp_regs += FloatRegSet::of(vm_reg->as_FloatRegister());
343+
} else {
344+
fatal("Unknown register type");
345+
}
346+
}
347+
}
348+
349+
// Remove C-ABI SOE registers, scratch regs and _ref register that will be updated
350+
_gp_regs -= RegSet::range(r23, r30) + RegSet::of(r3, r16, r19, stub->ref());
351+
}
352+
353+
ZSaveLiveRegisters(MacroAssembler* masm, ZLoadBarrierStubC2* stub) :
354+
_masm(masm),
355+
_gp_regs(),
356+
_fp_regs() {
357+
358+
// Figure out what registers to save/restore
359+
initialize(stub);
360+
361+
// Save registers
362+
__ push(_gp_regs);
363+
__ push_fpu(_fp_regs);
364+
}
365+
366+
~ZSaveLiveRegisters() {
367+
// Restore registers
368+
__ pop_fpu(_fp_regs);
369+
__ pop(_gp_regs);
370+
}
371+
};
372+
373+
#undef __
374+
#define __ _masm->
375+
322376
class ZSetupArguments {
323377
private:
324378
MacroAssembler* const _masm;
@@ -363,6 +417,13 @@ class ZSetupArguments {
363417
}
364418
}
365419
}
420+
421+
~ZSetupArguments() {
422+
// Transfer result
423+
if (_ref != V0) {
424+
__ move(_ref, V0);
425+
}
426+
}
366427
};
367428

368429
#undef __
@@ -374,23 +435,10 @@ void ZBarrierSetAssembler::generate_c2_load_barrier_stub(MacroAssembler* masm, Z
374435
// Stub entry
375436
__ bind(*stub->entry());
376437

377-
Register ref = stub->ref();
378-
379438
{
380-
if (ref != V0) {
381-
__ push(V0);
382-
}
383-
__ pushad_except_v0();
384-
439+
ZSaveLiveRegisters save_live_registers(masm, stub);
385440
ZSetupArguments setup_arguments(masm, stub);
386441
__ call_VM_leaf(stub->slow_path(), 2);
387-
388-
__ popad_except_v0();
389-
390-
if (ref != V0) {
391-
__ move(ref, V0);
392-
__ pop(V0);
393-
}
394442
}
395443
// Stub exit
396444
__ b(*stub->continuation());

src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@
2525

2626
#ifndef CPU_LOONGARCH_GLOBALDEFINITIONS_LOONGARCH_HPP
2727
#define CPU_LOONGARCH_GLOBALDEFINITIONS_LOONGARCH_HPP
28-
// Size of LOONGARCH Instructions
28+
// Size of LoongArch Instructions
2929
const int BytesPerInstWord = 4;
3030

3131
const int StackAlignmentInBytes = (2*wordSize);
@@ -48,8 +48,6 @@ const bool CCallingConventionRequiresIntsAsLongs = false;
4848

4949
#define SUPPORT_RESERVED_STACK_AREA
5050

51-
#define PREFERRED_METASPACE_ALIGNMENT
52-
5351
#define COMPRESSED_CLASS_POINTERS_DEPENDS_ON_COMPRESSED_OOPS false
5452

5553
#define USE_POINTERS_TO_REGISTER_IMPL_ARRAY

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