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Hikey960 upstream rebase #24

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2a1ac1c
document: dt: add binding for Hi3660 SoC
Dec 16, 2016
46f236d
arm64: dts: Add dts files for Hisilicon Hi3660 SoC
Dec 16, 2016
4495078
arm64: dts: hisilicon: add dtsi file for Hisilicon Hi3660 SOC
Jan 18, 2017
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4 changes: 4 additions & 0 deletions Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,10 @@ Hi6220 SoC
Required root node properties:
- compatible = "hisilicon,hi6220";

Hi3660 SoC
Required root node properties:
- compatible = "hisilicon,hi3660";

HiKey Board
Required root node properties:
- compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
Expand Down
63 changes: 63 additions & 0 deletions [PATCH 1_2] document dt add binding for Hi3660 SoC.eml
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14.3.235.1; Fri, 16 Dec 2016 15:50:28 +0800
From: Chen Feng <puck.chen@hisilicon.com>
To: <puck.chen@hisilicon.com>, <xuwei5@hisilicon.com>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <xuyiping@hisilicon.com>
CC: <suzhuangluan@hisilicon.com>, <haojian.zhuang@linaro.org>,
<guodong.xu@linaro.org>, <dan.zhao@hisilicon.com>,
<saberlily.xia@hisilicon.com>, <puck.chen@foxmail.com>,
<oliver.fu@hisilicon.com>, <xuhongtao8@hisilicon.com>
Subject: [PATCH 1/2] document: dt: add binding for Hi3660 SoC
Date: Fri, 16 Dec 2016 15:50:26 +0800
Message-ID: <1481874627-79760-1-git-send-email-puck.chen@hisilicon.com>
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Add binding for hisilicon Hi3660 SoC and HiKey960 Board.

Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
---
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 3f81575..7cf2847 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -8,6 +8,10 @@ Hi6220 SoC
Required root node properties:
- compatible = "hisilicon,hi6220";

+Hi3660 SoC
+Required root node properties:
+ - compatible = "hisilicon,hi3660";
+
HiKey Board
Required root node properties:
- compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
--
1.9.1


270 changes: 270 additions & 0 deletions [PATCH 2_2] arm64 dts Add dts files for Hisilicon Hi3660 SoC.eml
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From: Chen Feng <puck.chen@hisilicon.com>
To: <puck.chen@hisilicon.com>, <xuwei5@hisilicon.com>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <xuyiping@hisilicon.com>
CC: <suzhuangluan@hisilicon.com>, <haojian.zhuang@linaro.org>,
<guodong.xu@linaro.org>, <dan.zhao@hisilicon.com>,
<saberlily.xia@hisilicon.com>, <puck.chen@foxmail.com>,
<oliver.fu@hisilicon.com>, <xuhongtao8@hisilicon.com>
Subject: [PATCH 2/2] arm64: dts: Add dts files for Hisilicon Hi3660 SoC
Date: Fri, 16 Dec 2016 15:50:27 +0800
Message-ID: <1481874627-79760-2-git-send-email-puck.chen@hisilicon.com>
X-Mailer: git-send-email 1.9.1
In-Reply-To: <1481874627-79760-1-git-send-email-puck.chen@hisilicon.com>
References: <1481874627-79760-1-git-send-email-puck.chen@hisilicon.com>
MIME-Version: 1.0
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Add initial dtsi file to support Hisilicon Hi3660 SoC with
support of Octal core CPUs in two clusters(4 * A53 & 4 * A73).

Also add dts file to support HiKey960 development board which
based on Hi3660 SoC.
The output console is earlycon "earlycon=pl011,0xfdf05000".
And the con_init uart5 with a fixed clock, which already
configured at bootloader.

When clock is available, the uart5 will be modified.

Tested on HiKey960 Board.

Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
---
arch/arm64/boot/dts/hisilicon/Makefile | 1 +
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 37 +++++
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 156 ++++++++++++++++++++++
3 files changed, 194 insertions(+)
create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660.dtsi

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
new file mode 100644
index 0000000..9a1d36a
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -0,0 +1,37 @@
+/*
+ * dts file for Hisilicon HiKey960 Development Board
+ *
+ * Copyright (C) 2016, Hisilicon Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "hi3660.dtsi"
+/*#include "hi3660-ion.dtsi"*/
+/*#include "hikey960-pinctrl.dtsi"*/
+
+/ {
+ model = "HiKey960";
+ compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
+ hisi,boardid = <5 3 0 0>;
+
+ aliases {
+ serial5 = &uart5; /* console UART */
+ };
+
+ chosen {
+ stdout-path = "serial5:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x00400000 0x0 0xBFE00000>;
+ };
+
+ soc {
+ uart5: uart@fdf05000 {
+ status = "ok";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
new file mode 100644
index 0000000..399e084
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -0,0 +1,156 @@
+/*
+ * dts file for Hisilicon Hi3660 SoC
+ *
+ * Copyright (C) 2016, Hisilicon Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "hisilicon,hi3660";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+
+ cpu4: cpu@100 {
+ compatible = "arm,cortex-a73", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ };
+
+ cpu5: cpu@101 {
+ compatible = "arm,cortex-a73", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ };
+
+ cpu6: cpu@102 {
+ compatible = "arm,cortex-a73", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
+ };
+
+ cpu7: cpu@103 {
+ compatible = "arm,cortex-a73", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
+ };
+ };
+
+ gic: interrupt-controller@e82b0000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
+ <0x0 0xe82b2000 0 0x2000>, /* GICC */
+ <0x0 0xe82b4000 0 0x2000>, /* GICH */
+ <0x0 0xe82b6000 0 0x2000>; /* GICV */
+ #address-cells = <0>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <1920000>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ fixed_uart5: fixed_19_2M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ clock-output-names = "fixed:uart5";
+ };
+
+ uart5: uart@fdf05000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf05000 0x0 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&fixed_uart5 &fixed_uart5>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "ok";
+ };
+ };
+};
--
1.9.1


1 change: 1 addition & 0 deletions arch/arm64/boot/dts/hisilicon/Makefile
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb
dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
dtb-$(CONFIG_ARCH_HISI) += hip07-d05.dtb
Expand Down
36 changes: 36 additions & 0 deletions arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
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Original file line number Diff line number Diff line change
@@ -0,0 +1,36 @@
/*
* dts file for Hisilicon HiKey960 Development Board
*
* Copyright (C) 2016, Hisilicon Ltd.
*
*/

/dts-v1/;

#include "hi3660.dtsi"
#include "hikey960-pinctrl.dtsi"

/ {
model = "HiKey960";
compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
hisi,boardid = <5 3 0 0>;

aliases {
serial5 = &uart5; /* console UART */
};

chosen {
stdout-path = "serial5:115200n8";
};

memory@0 {
device_type = "memory";
reg = <0x0 0x00400000 0x0 0xBFE00000>;
};

soc {
uart5: uart@fdf05000 {
status = "ok";
};
};
};
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