feat(risc-v): first draft #3
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lethalNeutrino
requested changes
Nov 20, 2025
| - section: RISC-V | ||
| href: content/RISC-V/index.qmd | ||
| contents: | ||
| - href: content/RISC-V/instruction_formats.qmd |
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Make sure you add a href to content/RISC-V/index.qmd here:
| such as addition of two numbers or storing data to memory. Below is a comparison between RISCV code and its equivalent C code: | ||
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| ::: {layout-ncol=2} |
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Landrew layout nit: add tailwindcss
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| title: "RISC-V Instruction Formats" | ||
| subtitle: "UC Berkeley, CS 61C" |
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why is this like tripled
| **2. Which fields decide the ALU operation for R-type instructions?** | ||
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| ::: {.callout-note collapse="true" title="Check Answer"} | ||
| **funct3, funct7, and opcode.** |
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monospace funct3 etc.
| ::: {.callout-note collapse="true" title="Check Answer"} | ||
| **funct3, funct7, and opcode.** | ||
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| While the opcode identifies the instruction as R-Type, the `funct` fields select the specific operation (Add vs Sub vs Xor). |
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| ### Conceptual Pre-Check | ||
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| **1.1 True or False: The opcode field determines the instruction type (R, I, I$\star$, S, etc.).** |
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you should just use an asterisk instead of
| #### R-Type: Register Operations | ||
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| **Structure:** | ||
| ``` |
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Make this into a table possbly a @lethalNeutrino
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| ### Format Summary Table | ||
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| | Format | Registers | Immediate Bits | Use Case | Example | |
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Run markdown formatter on these tables
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