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The T80 (VHDL) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,t80)

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playing around with (V)HDL and the T80 from OpenCores (a Z80/8080 clone)

=============

most of the work/play is done in bench/vhdl
there is a Makefile there

$ make clean; make
$ ./testbench --stop-time=16ms --wave=testbench.ghw
$ cat RX_Log.txt


Simple Z80-monitor - V 0.8 (B. Ulmann, Sep. 2011 - Jan. 2012)
Cold start, clearing memory.


depending on the value of "--stop-time" there can be more or less
text logged in the RX_Log.txt file.

=============

supporting files:

[1] z80mon.asm
from the zasm [https://github.com/Megatokio/zasm] repo
https://github.com/Megatokio/zasm/blob/master/Test/Z80/z80mon.asm

compiled with:
zasm -x z80mon.asm

which generates 2 files
z80mon.hex
z80mon.lst

the z80mon.hex is used below.


[2] ROM80.vhd
is generated by hex2rom
https://github.com/167rgc911/t80/blob/master/sw/hex2rom.cpp

compiled with:
g++ hex2rom.cpp -o hex2rom 

put the executable in a directory in your $PATH

generating ROM80.vhd requires executing:
hex2rom z80mon.hex ROM80 15l8z > ROM80.vhd

=============

todo:
implement the idea in https://github.com/167rgc911/puart
to allow a serial comms program (ie picocom) to "connect" to
the UART

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The T80 (VHDL) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,t80)

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  • VHDL 72.0%
  • Assembly 20.3%
  • C++ 6.3%
  • Batchfile 0.6%
  • Tcl 0.5%
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