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instrs.txt
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instrs.txt
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# Fadec Instruction Description Table
#
# This file table contains all supported instructions. The format is custom,
# this parsed and processed into decode tables/encoders in parseinstrs.py.
#
#
# The opcode is used to determine the instruction row when decoding from
# instruction bytes. There are multiple components up to the opcode byte:
#
# (VEX\.|EVEX\.)? -> VEX/EVEX prefix; or legacy if absent
# ((NP|66|F2|F3|NFx)\.)? -> optional mandatory prefix
# (W[01]\.)? -> W0/W1, ignored if absent
# (L(0|1|12|IG)\.)? -> VEX.L/EVEX.L'L constraint, must not occur for legacy
# opcodes; not really used for distinguishing instructions/encodings
# (exceptions: VZEROUPPER/VZEROALL and VMOVDDUP)
# (|0f|0f38|0f3a|M[56]\.) -> legacy escape; or VEX/EVEX opcode map
# [0-9a-f]{2} -> actual opcode byte
#
# After the opcode byte, at most one of the following specifiers can follow:
#
# /[rm] -> ModRM.mod specifier (register or memory operand only)
# /[0-7] -> ModRM.reg specifier (used as opcode extension)
# /[0-7][rm] -> ModRM.mod and ModRM.reg specifier
# /[rm][0-7] -> ModRM.mod and ModRM.r/m specifier (AMX only)
# [c-f][0-9a-f] -> complete ModRM specifier, whole byte used as opcode ext.
# + -> for O-encoded instructions, the last three bits are an operand
#
# A legacy opcode may be prefixed with "*", making it a weak opcode which can be
# overwritten by later opcode definitions. This is used for reserved nops,
# reserved prefetch, BSF/BSR (overwritten by TZCNT/LZCNT), and WBINVD
# (overwritten by WBNOINVD).
#
# The encoding description follows the naming found in older (pre-AVX-512) Intel
# SDMs. It maps encoding fields to operand indices and specifies the immediate
# encoding. The gist is: M=ModRM.r/m; R=ModRM.reg; V=VEX.vvvv; A=EAX/XMM0; C=CL;
# I=imm; O=opcode bits 5:7; S=opcode bits 2:4; FD/TD=absolute address; D=jump
# destination. RVMR is an exception, the register is encoded in imm8[7:4].
# MOV_CR/MOV_DR are another exception, they ignore ModRM.mod and always encode a
# register operand.
#
# For operands, the first letter specified the operand kind. Naming is mostly
# consistent with Intel's SDM, except for F (Intel: eflags; here: FPU).
#
# GP MMX XMM MSK TMM FPU CR DR SEG
# ModRM.r/m (reg) R N U K T F - - -
# ModRM.r/m (r/m) E Q W K T - - - -
# ModRM.reg G P V K T F C D S
# VEX.vvvv B - H K T - - - -
# imm8[7:4] - - L - - - - - -
#
# M=memory only; O=direct address
# I=immediate; A=address/far jmp; J=rip-relative address/jmp
#
# The remaining one or two letters specify the operand size:
#
# - Fixed sizes: b=1; w=2, d/ss=4; q/sd=8; dq=16; qq=32; oq=64
# - GP operand sizes: v=2/4/8 (66/REX.W); y=4/8 (66 ignored)
# - Vector sizes: x/ps/pd=16/32/64 (EVEX.L'L); h=half x, f=fourth x; e=eighth x
# - Other immediate sizes: z=v with max. 4 bytes; bs=v (sign-extended byte);
# zd=z (but always four byte imm); zq=z (but always eight byte imm)
# - Special operand size: a=z:z (BOUND only); p=w:z (far pointer)
# - If not letter is specified, the operand size is decoded as zero. The size
# is implicitly part of the operand and can be reconstructed by the user.
#
# The instruction mnemonic is generally specified as decoded/formatted (there
# are a few exceptions, see parseinstrs.py decode_table and encode_mnems).
#
# After the mnemonic, flags can be specified. Some common flags have a short
# form immediately after the mnemonic (e.g., EVX_ADDSD+kr), others do not.
#
# - I64: invalid in 64-bit mode
# - O64: only valid in 64-bit mode
# - +w (INSTR_WIDTH): store operand size as instruction attribute; used for
# instructions that depend on the operand size but have no explicit operands.
# - +a (U67): respects addr-size override even without memory operand.
# - +s (USEG): respects segment override even without memory operand.
# - +k (MASK): supports EVEX masking.
# - +e (SAE): supports EVEX suppress all exceptions.
# - +r (ER): supports EVEX embedded rounding control.
# - +b (BCST): supports EVEX embedded broadcast. Broadcast size depends on REX.W
# (REX.W=0 => 32 bits; REX.W=1 => 64 bits).
# - BCST16: set EVEX embedded broadcast size to 16 bits.
# - SZ8: has effective operand size of 8 bits (encode only).
# - U66: uses 66 prefix as operand size override even with a mandatory prefix.
# - I66: ignores 66 prefix as operand size override.
# - LOCK: supports LOCK prefix when the first operand is memory.
# - D64: defaults to 64-bit operand size in 64-bit mode (REX.W ignored).
# - F64: forced to 64-bit operand size in 64-bit mode (66/REX.W ignored).
# NB: this is Intel-specific. On AMD, F64 behaves like D64.
# - VSIB: memory operand uses VSIB encoding (SIB required, idx is vector).
# - ENC_SEPSZ: attach size suffixes to each operand (encode only).
# - ENC_NOSZ: do not attach size suffix (encode only).
# - ENC_REP: supports REP prefix.
# - ENC_REPCC: supports REPZ/REPNZ prefix.
# - UNDOC: undocumented, ignored by default.
# - TUPLE_*: AVX-512 tuple size. Only used to verify operand sizes.
# - CPL0: only valid if CPL=0 (system mode). Annotation only.
# - F=<feature flags>: feature flags. Annotation only.
# - EFL=<flags>: status flags use/modifications. Order: OF/DF/IF/SF/ZF/AF/PF/CF.
# t=test; m=modify; 0=clear; 1=set; M=test-and-modify; u=undefined
#
#
# Opcode ENC OP1 OP2 OP3 OP4 MNEM COND SZ? MISC FLAGS
# LOCK SZ8
# I64 D64
# O64 F64
# VSIB U66
# I66
# ------------------- ---- --- --- --- --- ------- ---- --- ----------
00 MR Eb Gb - - ADD LOCK SZ8 EFL=m--mmmmm
01 MR Ev Gv - - ADD LOCK EFL=m--mmmmm
02 RM Gb Eb - - ADD SZ8 EFL=m--mmmmm
03 RM Gv Ev - - ADD EFL=m--mmmmm
04 IA Rb Ib - - ADD SZ8 EFL=m--mmmmm
05 IA Rv Iz - - ADD EFL=m--mmmmm
06 S Sv - - - PUSH_SEG I64
07 S Sv - - - POP_SEG I64
08 MR Eb Gb - - OR LOCK SZ8 EFL=0--mmum0
09 MR Ev Gv - - OR LOCK EFL=0--mmum0
0a RM Gb Eb - - OR SZ8 EFL=0--mmum0
0b RM Gv Ev - - OR EFL=0--mmum0
0c IA Rb Ib - - OR SZ8 EFL=0--mmum0
0d IA Rv Iz - - OR EFL=0--mmum0
0e S Sv - - - PUSH_SEG I64
#0f escape opcode
10 MR Eb Gb - - ADC LOCK SZ8 EFL=m--mmmmM
11 MR Ev Gv - - ADC LOCK EFL=m--mmmmM
12 RM Gb Eb - - ADC SZ8 EFL=m--mmmmM
13 RM Gv Ev - - ADC EFL=m--mmmmM
14 IA Rb Ib - - ADC SZ8 EFL=m--mmmmM
15 IA Rv Iz - - ADC EFL=m--mmmmM
16 S Sv - - - PUSH_SEG I64
17 S Sv - - - POP_SEG I64
18 MR Eb Gb - - SBB LOCK SZ8 EFL=m--mmmmM
19 MR Ev Gv - - SBB LOCK EFL=m--mmmmM
1a RM Gb Eb - - SBB SZ8 EFL=m--mmmmM
1b RM Gv Ev - - SBB EFL=m--mmmmM
1c IA Rb Ib - - SBB SZ8 EFL=m--mmmmM
1d IA Rv Iz - - SBB EFL=m--mmmmM
1e S Sv - - - PUSH_SEG I64
1f S Sv - - - POP_SEG I64
20 MR Eb Gb - - AND LOCK SZ8 EFL=0--mmum0
21 MR Ev Gv - - AND LOCK EFL=0--mmum0
22 RM Gb Eb - - AND SZ8 EFL=0--mmum0
23 RM Gv Ev - - AND EFL=0--mmum0
24 IA Rb Ib - - AND SZ8 EFL=0--mmum0
25 IA Rv Iz - - AND EFL=0--mmum0
#26 SEG=ES prefix
27 NP - - - - DAA I64 EFL=u--mmMmM
28 MR Eb Gb - - SUB LOCK SZ8 EFL=m--mmmmm
29 MR Ev Gv - - SUB LOCK EFL=m--mmmmm
2a RM Gb Eb - - SUB SZ8 EFL=m--mmmmm
2b RM Gv Ev - - SUB EFL=m--mmmmm
2c IA Rb Ib - - SUB SZ8 EFL=m--mmmmm
2d IA Rv Iz - - SUB EFL=m--mmmmm
#2e SEG=CS prefix
2f NP - - - - DAS I64 EFL=u--mmMmM
30 MR Eb Gb - - XOR LOCK SZ8 EFL=0--mmum0
31 MR Ev Gv - - XOR LOCK EFL=0--mmum0
32 RM Gb Eb - - XOR SZ8 EFL=0--mmum0
33 RM Gv Ev - - XOR EFL=0--mmum0
34 IA Rb Ib - - XOR SZ8 EFL=0--mmum0
35 IA Rv Iz - - XOR EFL=0--mmum0
#36 SEG=SS prefix
37 NP - - - - AAA I64 EFL=u--uuMum
38 MR Eb Gb - - CMP SZ8 EFL=m--mmmmm
39 MR Ev Gv - - CMP EFL=m--mmmmm
3a RM Gb Eb - - CMP SZ8 EFL=m--mmmmm
3b RM Gv Ev - - CMP EFL=m--mmmmm
3c IA Rb Ib - - CMP SZ8 EFL=m--mmmmm
3d IA Rv Iz - - CMP EFL=m--mmmmm
#3e SEG=DS prefix
3f NP - - - - AAS I64 EFL=u--uuMum
40+ O Rv - - - INC I64 EFL=m--mmmm-
48+ O Rv - - - DEC I64 EFL=m--mmmm-
50+ O Rv - - - PUSH D64
58+ O Rv - - - POP D64
60 NP - - - - PUSHA+w I64
61 NP - - - - POPA+w I64
62/m RM Gv Ma - - BOUND I64
63 MR Ew Gw - - ARPL I64 EFL=----m---
63 RM Gv Ed - - MOVSX O64 F=LM ENC_SEPSZ
#64 SEG=FS prefix
#65 SEG=GS prefix
#66 operand size prefix
#67 address size prefix
68 I Iz - - - PUSH D64
69 RMI Gv Ev Iz - IMUL EFL=m--uuuum
6a I Ibs - - - PUSH D64
6b RMI Gv Ev Ibs - IMUL EFL=m--uuuum
6c NP - - - - INS+wa SZ8 ENC_REP EFL=-t------
6d NP - - - - INS+wa ENC_REP EFL=-t------
6e NP - - - - OUTS+was SZ8 ENC_REP EFL=-t------
6f NP - - - - OUTS+was ENC_REP EFL=-t------
70 D Jbs - - - JO F64 EFL=t-------
71 D Jbs - - - JNO F64 EFL=t-------
72 D Jbs - - - JC F64 EFL=-------t
73 D Jbs - - - JNC F64 EFL=-------t
74 D Jbs - - - JZ F64 EFL=----t---
75 D Jbs - - - JNZ F64 EFL=----t---
76 D Jbs - - - JBE F64 EFL=----t--t
77 D Jbs - - - JA F64 EFL=----t--t
78 D Jbs - - - JS F64 EFL=---t----
79 D Jbs - - - JNS F64 EFL=---t----
7a D Jbs - - - JP F64 EFL=------t-
7b D Jbs - - - JNP F64 EFL=------t-
7c D Jbs - - - JL F64 EFL=t--t----
7d D Jbs - - - JGE F64 EFL=t--t----
7e D Jbs - - - JLE F64 EFL=t--tt---
7f D Jbs - - - JG F64 EFL=t--tt---
80/0 MI Eb Ib - - ADD LOCK SZ8 EFL=m--mmmmm
80/1 MI Eb Ib - - OR LOCK SZ8 EFL=0--mmum0
80/2 MI Eb Ib - - ADC LOCK SZ8 EFL=m--mmmmM
80/3 MI Eb Ib - - SBB LOCK SZ8 EFL=m--mmmmM
80/4 MI Eb Ib - - AND LOCK SZ8 EFL=0--mmum0
80/5 MI Eb Ib - - SUB LOCK SZ8 EFL=m--mmmmm
80/6 MI Eb Ib - - XOR LOCK SZ8 EFL=0--mmum0
80/7 MI Eb Ib - - CMP SZ8 EFL=m--mmmmm
81/0 MI Ev Iz - - ADD LOCK EFL=m--mmmmm
81/1 MI Ev Iz - - OR LOCK EFL=0--mmum0
81/2 MI Ev Iz - - ADC LOCK EFL=m--mmmmM
81/3 MI Ev Iz - - SBB LOCK EFL=m--mmmmM
81/4 MI Ev Iz - - AND LOCK EFL=0--mmum0
81/5 MI Ev Iz - - SUB LOCK EFL=m--mmmmm
81/6 MI Ev Iz - - XOR LOCK EFL=0--mmum0
81/7 MI Ev Iz - - CMP EFL=m--mmmmm
82/0 MI Eb Ib - - ADD LOCK I64 SZ8 EFL=m--mmmmm
82/1 MI Eb Ib - - OR LOCK I64 SZ8 EFL=0--mmum0
82/2 MI Eb Ib - - ADC LOCK I64 SZ8 EFL=m--mmmmM
82/3 MI Eb Ib - - SBB LOCK I64 SZ8 EFL=m--mmmmM
82/4 MI Eb Ib - - AND LOCK I64 SZ8 EFL=0--mmum0
82/5 MI Eb Ib - - SUB LOCK I64 SZ8 EFL=m--mmmmm
82/6 MI Eb Ib - - XOR LOCK I64 SZ8 EFL=0--mmum0
82/7 MI Eb Ib - - CMP I64 SZ8 EFL=m--mmmmm
83/0 MI Ev Ibs - - ADD LOCK EFL=m--mmmmm
83/1 MI Ev Ibs - - OR LOCK EFL=0--mmum0
83/2 MI Ev Ibs - - ADC LOCK EFL=m--mmmmM
83/3 MI Ev Ibs - - SBB LOCK EFL=m--mmmmM
83/4 MI Ev Ibs - - AND LOCK EFL=0--mmum0
83/5 MI Ev Ibs - - SUB LOCK EFL=m--mmmmm
83/6 MI Ev Ibs - - XOR LOCK EFL=0--mmum0
83/7 MI Ev Ibs - - CMP EFL=m--mmmmm
84 MR Eb Gb - - TEST SZ8 EFL=0--mmum0
85 MR Ev Gv - - TEST EFL=0--mmum0
86 MR Eb Gb - - XCHG LOCK SZ8
87 MR Ev Gv - - XCHG LOCK
88 MR Eb Gb - - MOV SZ8
89 MR Ev Gv - - MOV
8a RM Gb Eb - - MOV SZ8
8b RM Gv Ev - - MOV
# TODO: 8c is actually Ev,Sw; exact semantics are TBD
8c/0 MR Ew Sw - - MOV_S2G
8c/1 MR Ew Sw - - MOV_S2G
8c/2 MR Ew Sw - - MOV_S2G
8c/3 MR Ew Sw - - MOV_S2G
8c/4 MR Ew Sw - - MOV_S2G
8c/5 MR Ew Sw - - MOV_S2G
8d/m RM Gv M - - LEA
8e/0 RM Sw Ew - - MOV_G2S
8e/2 RM Sw Ew - - MOV_G2S
8e/3 RM Sw Ew - - MOV_G2S
8e/4 RM Sw Ew - - MOV_G2S
8e/5 RM Sw Ew - - MOV_G2S
8f/0 M Ev - - - POP D64
# Against frequent belief, only, XCHG (r/e)AX, (r)AX with 90 is NOP.
# As a lacking REX.B cannot be specified here, this is hardcoded.
90+ OA Rv Rv - - XCHG_NOP
98 NP - - - - C_EX+w
99 NP - - - - C_SEP+w
# Far jmp/call immediate size adjusted in code
9a I Ap - - - CALLF I64
9b NP - - - - FWAIT
9c NP - - - - PUSHF+w D64 EFL=tttttttt
9d NP - - - - POPF+w D64 EFL=mmmmmmmm
9e NP - - - - SAHF EFL=---mmmmm
9f NP - - - - LAHF EFL=---ttttt
a0 FD Rb Ob - - MOV+as SZ8
a1 FD Rv Ov - - MOV+as
a2 TD Ob Rb - - MOV+as SZ8
a3 TD Ov Rv - - MOV+as
a4 NP - - - - MOVS+was SZ8 ENC_REP EFL=-t------
a5 NP - - - - MOVS+was ENC_REP EFL=-t------
a6 NP - - - - CMPS+was SZ8 ENC_REPCC EFL=mt-mmmmm
a7 NP - - - - CMPS+was ENC_REPCC EFL=mt-mmmmm
a8 IA Rb Ib - - TEST SZ8 EFL=0--mmum0
a9 IA Rv Iz - - TEST EFL=0--mmum0
aa NP - - - - STOS+wa SZ8 ENC_REP EFL=-t------
ab NP - - - - STOS+wa ENC_REP EFL=-t------
ac NP - - - - LODS+was SZ8 ENC_REP EFL=-t------
ad NP - - - - LODS+was ENC_REP EFL=-t------
ae NP - - - - SCAS+wa SZ8 ENC_REPCC EFL=mt-mmmmm
af NP - - - - SCAS+wa ENC_REPCC EFL=mt-mmmmm
b0+ OI Rb Ib - - MOVABS SZ8
b8+ OI Rv Iv - - MOVABS
c0/0 MI Eb Ib - - ROL SZ8 EFL=m------m
c0/1 MI Eb Ib - - ROR SZ8 EFL=m------m
c0/2 MI Eb Ib - - RCL SZ8 EFL=m------M
c0/3 MI Eb Ib - - RCR SZ8 EFL=m------M
c0/4 MI Eb Ib - - SHL SZ8 EFL=m--mmumm
c0/5 MI Eb Ib - - SHR SZ8 EFL=m--mmumm
c0/6 MI Eb Ib - - SHL SZ8 EFL=m--mmumm
c0/7 MI Eb Ib - - SAR SZ8 EFL=m--mmumm
c1/0 MI Ev Ib - - ROL EFL=m------m
c1/1 MI Ev Ib - - ROR EFL=m------m
c1/2 MI Ev Ib - - RCL EFL=m------M
c1/3 MI Ev Ib - - RCR EFL=m------M
c1/4 MI Ev Ib - - SHL EFL=m--mmumm
c1/5 MI Ev Ib - - SHR EFL=m--mmumm
c1/6 MI Ev Ib - - SHL EFL=m--mmumm
c1/7 MI Ev Ib - - SAR EFL=m--mmumm
# RET immediate size handled in code
c2 I Iw - - - RET+w F64
c3 NP - - - - RET+w F64
c4/m RM Gv Mp - - LES I64
c5/m RM Gv Mp - - LDS I64
c6/0 MI Eb Ib - - MOV SZ8
c6f8 I Ib - - - XABORT F=HLERTM
c7/0 MI Ev Iz - - MOV
c7f8 D Jzd - - - XBEGIN I64 F=HLERTM
c7f8 D Jzq - - - XBEGIN O64 F=HLERTM
# ENTER immediate handled in code, actually it is Iw,Ib
c8 I Id - - - ENTER+w D64
c9 NP - - - - LEAVE+w D64
# RETF immediate size handled in code
ca I Iw - - - RETF+w
cb NP - - - - RETF+w
cc NP - - - - INT3 EFL=--M-----
cd I Ib - - - INT EFL=--M-----
ce NP - - - - INTO I64 EFL=t-M-----
cf NP - - - - IRET+w EFL=mmmmmmmm
d0/0 M1 Eb Ib - - ROL SZ8 EFL=m------m
d0/1 M1 Eb Ib - - ROR SZ8 EFL=m------m
d0/2 M1 Eb Ib - - RCL SZ8 EFL=m------M
d0/3 M1 Eb Ib - - RCR SZ8 EFL=m------M
d0/4 M1 Eb Ib - - SHL SZ8 EFL=m--mmumm
d0/5 M1 Eb Ib - - SHR SZ8 EFL=m--mmumm
d0/6 M1 Eb Ib - - SHL SZ8 EFL=m--mmumm
d0/7 M1 Eb Ib - - SAR SZ8 EFL=m--mmumm
d1/0 M1 Ev Ib - - ROL EFL=m------m
d1/1 M1 Ev Ib - - ROR EFL=m------m
d1/2 M1 Ev Ib - - RCL EFL=m------M
d1/3 M1 Ev Ib - - RCR EFL=m------M
d1/4 M1 Ev Ib - - SHL EFL=m--mmumm
d1/5 M1 Ev Ib - - SHR EFL=m--mmumm
d1/6 M1 Ev Ib - - SHL EFL=m--mmumm
d1/7 M1 Ev Ib - - SAR EFL=m--mmumm
d2/0 MC Eb Rb - - ROL SZ8 EFL=m------m
d2/1 MC Eb Rb - - ROR SZ8 EFL=m------m
d2/2 MC Eb Rb - - RCL SZ8 EFL=m------M
d2/3 MC Eb Rb - - RCR SZ8 EFL=m------M
d2/4 MC Eb Rb - - SHL SZ8 EFL=m--mmumm
d2/5 MC Eb Rb - - SHR SZ8 EFL=m--mmumm
d2/6 MC Eb Rb - - SHL SZ8 EFL=m--mmumm
d2/7 MC Eb Rb - - SAR SZ8 EFL=m--mmumm
d3/0 MC Ev Rb - - ROL EFL=m------m
d3/1 MC Ev Rb - - ROR EFL=m------m
d3/2 MC Ev Rb - - RCL EFL=m------M
d3/3 MC Ev Rb - - RCR EFL=m------M
d3/4 MC Ev Rb - - SHL EFL=m--mmumm
d3/5 MC Ev Rb - - SHR EFL=m--mmumm
d3/6 MC Ev Rb - - SHL EFL=m--mmumm
d3/7 MC Ev Rb - - SAR EFL=m--mmumm
d4 I Ib - - - AAM I64 SZ8 EFL=u--mmumu
d5 I Ib - - - AAD I64 SZ8 EFL=u--mmumu
d6 NP - - - - SALC I64 UNDOC
d7 NP - - - - XLATB+as
#d8-df FPU Escape
e0 D Jbs - - - LOOPNZ+a F64 EFL=----t---
e1 D Jbs - - - LOOPZ+a F64 EFL=----t---
e2 D Jbs - - - LOOP+a F64
e3 D Jbs - - - JCXZ+a F64
e4 IA Rb Ib - - IN SZ8
e5 IA Rz Ib - - IN
e6 IA Rb Ib - - OUT SZ8
e7 IA Rz Ib - - OUT
e8 D Jz - - - CALL F64
e9 D Jz - - - JMP F64
# Far jmp/call immediate size adjusted in code
ea I Ap - - - JMPF I64
eb D Jbs - - - JMP F64
ec NP - - - - IN+w SZ8
ed NP - - - - IN+w
ee NP - - - - OUT+w SZ8
ef NP - - - - OUT+w
#f0 prefix
f1 NP - - - - INT1 EFL=--M-----
#f2 REPNZ prefix
#f3 REP/REPZ prefix
f4 NP - - - - HLT CPL0
f5 NP - - - - CMC EFL=-------M
f6/0 MI Eb Ib - - TEST SZ8 EFL=0--mmum0
f6/1 MI Eb Ib - - TEST SZ8 EFL=0--mmum0
f6/2 M Eb - - - NOT LOCK SZ8
f6/3 M Eb - - - NEG LOCK SZ8 EFL=m--mmmmm
f6/4 M Eb - - - MUL SZ8 EFL=m--uuuum
f6/5 M Eb - - - IMUL SZ8 EFL=m--uuuum
f6/6 M Eb - - - DIV SZ8 EFL=u--uuuuu
f6/7 M Eb - - - IDIV SZ8 EFL=u--uuuuu
f7/0 MI Ev Iz - - TEST EFL=0--mmum0
f7/1 MI Ev Iz - - TEST EFL=0--mmum0
f7/2 M Ev - - - NOT LOCK
f7/3 M Ev - - - NEG LOCK EFL=m--mmmmm
f7/4 M Ev - - - MUL EFL=m--uuuum
f7/5 M Ev - - - IMUL EFL=m--uuuum
f7/6 M Ev - - - DIV EFL=u--uuuuu
f7/7 M Ev - - - IDIV EFL=u--uuuuu
f8 NP - - - - CLC EFL=-------0
f9 NP - - - - STC EFL=-------1
fa NP - - - - CLI EFL=--0-----
fb NP - - - - STI EFL=--1-----
fc NP - - - - CLD EFL=-0------
fd NP - - - - STD EFL=-1------
fe/0 M Eb - - - INC LOCK SZ8 EFL=m--mmmm-
fe/1 M Eb - - - DEC LOCK SZ8 EFL=m--mmmm-
ff/0 M Ev - - - INC LOCK EFL=m--mmmm-
ff/1 M Ev - - - DEC LOCK EFL=m--mmmm-
ff/2 M Ev - - - CALL F64
ff/3m M Mp - - - CALLF
ff/4 M Ev - - - JMP F64
ff/5m M Mp - - - JMPF
ff/6 M Ev - - - PUSH D64
# TODO: SDM states taht SLDT/STR are Rv/Mw (like SMSW), but semantics not verified
0f00/0 M Ew - - - SLDT
0f00/1 M Ew - - - STR
0f00/2 M Ew - - - LLDT CPL0
0f00/3 M Ew - - - LTR CPL0
0f00/4 M Ew - - - VERR EFL=----m---
0f00/5 M Ew - - - VERW EFL=----m---
0f01/0m M M - - - SGDT
0f01/1m M M - - - SIDT
0f01/2m M M - - - LGDT CPL0
0f01/3m M M - - - LIDT CPL0
0f01/4m M Mw - - - SMSW
0f01/4r M Rv - - - SMSW
0f01/6 M Ew - - - LMSW CPL0
0f01/7m M Mb - - - INVLPG SZ8 F=486 CPL0
NP.0f01c0 NP - - - - ENCLV F=SGX
NP.0f01c8 NP - - - - MONITOR F=MONITOR
NP.0f01c9 NP - - - - MWAIT F=MONITOR
NP.0f01ca NP - - - - CLAC F=SMAP CPL0
NP.0f01cb NP - - - - STAC F=SMAP CPL0
NP.0f01cf NP - - - - ENCLS F=SGX
NP.0f01d0 NP - - - - XGETBV F=XSAVE
NP.0f01d1 NP - - - - XSETBV F=XSAVE
NP.0f01d5 NP - - - - XEND F=HLERTM
NP.0f01d6 NP - - - - XTEST F=HLERTM EFL=0--0m000
NP.0f01d7 NP - - - - ENCLU F=SGX
0f01f8 NP - - - - SWAPGS O64 F=LM
0f01f9 NP - - - - RDTSCP F=RDTSCP
0f02 RM Gv Ew - - LAR EFL=----m---
0f03 RM Gv Ew - - LSL EFL=----m---
0f05 NP - - - - SYSCALL O64 F=LM EFL=MMMMMMMM
0f06 NP - - - - CLTS CPL0
0f07 NP - - - - SYSRET O64 F=LM CPL0 EFL=mmmmmmmm
0f08 NP - - - - INVD F=486 CPL0
*0f09 NP - - - - WBINVD F=486 CPL0
0f0b NP - - - - UD2
0f0d/0m M Mb - - - PREFETCH F=PREFETCH
0f0d/1m M Mb - - - PREFETCHW F=PREFETCHW
0f0d/2m M Mb - - - PREFETCHWT1 F=PREFETCHWT1
# All other slots are reserved, AMD maps them to /0
*0f0d/m M Mb - - - RESERVED_PREFETCH ONLYAMD F=PREFETCH
*0f0d/r MR Rv Gv - - RESERVED_NOP
0f0e NP - - - - FEMMS ONLYAMD F=3DNOW
# TODO: actually decode 3DNow! instructions. Given that 3DNow! no longer exists,
# this is unlikely to happen, though.
0f0f RMI Pq Qq Ib - 3DNOW ONLYAMD F=3DNOW
0f18/0m M Mb - - - PREFETCHNTA F=SSE
0f18/1m M Mb - - - PREFETCHT0 F=SSE
0f18/2m M Mb - - - PREFETCHT1 F=SSE
0f18/3m M Mb - - - PREFETCHT2 F=SSE
0f18/6m M Mb - - - PREFETCHIT1 O64 F=PREFETCHI
0f18/7m M Mb - - - PREFETCHIT0 O64 F=PREFETCHI
# Reserved NOPs are weak, they can be overridden by other instructions.
*0f18 MR Ev Gv - - RESERVED_NOP
*0f19 MR Ev Gv - - RESERVED_NOP
*0f1a MR Ev Gv - - RESERVED_NOP
*0f1b MR Ev Gv - - RESERVED_NOP
*0f1c MR Ev Gv - - RESERVED_NOP
*0f1d MR Ev Gv - - RESERVED_NOP
*0f1e MR Ev Gv - - RESERVED_NOP
*0f1f MR Ev Gv - - RESERVED_NOP
0f1f/0 M Ev - - - NOP
0f20 MR Ry Cy - - MOV_CR2G I66 D64 CPL0 EFL=u--uuuuu
0f21 MR Ry Dy - - MOV_DR2G I66 D64 CPL0 EFL=u--uuuuu
0f22 RM Cy Ry - - MOV_G2CR I66 D64 CPL0 EFL=u--uuuuu
0f23 RM Dy Ry - - MOV_G2DR I66 D64 CPL0 EFL=u--uuuuu
0f30 NP - - - - WRMSR F=586 CPL0
0f31 NP - - - - RDTSC F=586
0f32 NP - - - - RDMSR F=586 CPL0
0f33 NP - - - - RDPMC F=686
0f34 NP - - - - SYSENTER F=686 EFL=--m-----
0f35 NP - - - - SYSEXIT F=686 CPL0
NP.0f37 NP - - - - GETSEC F=SMX EFL=MMMMMMMM
# 0f38, 0f3a are escape opcodes
0f40 RM Gv Ev - - CMOVO F=CMOV EFL=t-------
0f41 RM Gv Ev - - CMOVNO F=CMOV EFL=t-------
0f42 RM Gv Ev - - CMOVC F=CMOV EFL=-------t
0f43 RM Gv Ev - - CMOVNC F=CMOV EFL=-------t
0f44 RM Gv Ev - - CMOVZ F=CMOV EFL=----t---
0f45 RM Gv Ev - - CMOVNZ F=CMOV EFL=----t---
0f46 RM Gv Ev - - CMOVBE F=CMOV EFL=----t--t
0f47 RM Gv Ev - - CMOVA F=CMOV EFL=----t--t
0f48 RM Gv Ev - - CMOVS F=CMOV EFL=---t----
0f49 RM Gv Ev - - CMOVNS F=CMOV EFL=---t----
0f4a RM Gv Ev - - CMOVP F=CMOV EFL=------t-
0f4b RM Gv Ev - - CMOVNP F=CMOV EFL=------t-
0f4c RM Gv Ev - - CMOVL F=CMOV EFL=t--t----
0f4d RM Gv Ev - - CMOVGE F=CMOV EFL=t--t----
0f4e RM Gv Ev - - CMOVLE F=CMOV EFL=t--tt---
0f4f RM Gv Ev - - CMOVG F=CMOV EFL=t--tt---
0f80 D Jz - - - JO F64 EFL=t-------
0f81 D Jz - - - JNO F64 EFL=t-------
0f82 D Jz - - - JC F64 EFL=-------t
0f83 D Jz - - - JNC F64 EFL=-------t
0f84 D Jz - - - JZ F64 EFL=----t---
0f85 D Jz - - - JNZ F64 EFL=----t---
0f86 D Jz - - - JBE F64 EFL=----t--t
0f87 D Jz - - - JA F64 EFL=----t--t
0f88 D Jz - - - JS F64 EFL=---t----
0f89 D Jz - - - JNS F64 EFL=---t----
0f8a D Jz - - - JP F64 EFL=------t-
0f8b D Jz - - - JNP F64 EFL=------t-
0f8c D Jz - - - JL F64 EFL=t--t----
0f8d D Jz - - - JGE F64 EFL=t--t----
0f8e D Jz - - - JLE F64 EFL=t--tt---
0f8f D Jz - - - JG F64 EFL=t--tt---
0f90 M Eb - - - SETO SZ8 EFL=t-------
0f91 M Eb - - - SETNO SZ8 EFL=t-------
0f92 M Eb - - - SETC SZ8 EFL=-------t
0f93 M Eb - - - SETNC SZ8 EFL=-------t
0f94 M Eb - - - SETZ SZ8 EFL=----t---
0f95 M Eb - - - SETNZ SZ8 EFL=----t---
0f96 M Eb - - - SETBE SZ8 EFL=----t--t
0f97 M Eb - - - SETA SZ8 EFL=----t--t
0f98 M Eb - - - SETS SZ8 EFL=---t----
0f99 M Eb - - - SETNS SZ8 EFL=---t----
0f9a M Eb - - - SETP SZ8 EFL=------t-
0f9b M Eb - - - SETNP SZ8 EFL=------t-
0f9c M Eb - - - SETL SZ8 EFL=t--t----
0f9d M Eb - - - SETGE SZ8 EFL=t--t----
0f9e M Eb - - - SETLE SZ8 EFL=t--tt---
0f9f M Eb - - - SETG SZ8 EFL=t--tt---
0fa0 S Sv - - - PUSH_SEG D64
0fa1 S Sv - - - POP_SEG D64
0fa2 NP - - - - CPUID F=586
0fa3 MR Ev Gv - - BT EFL=u--u-uum
0fa4 MRI Ev Gv Ib - SHLD EFL=u--mmumm
0fa5 MRC Ev Gv Rb - SHLD EFL=u--mmumm
0fa8 S Sv - - - PUSH_SEG D64
0fa9 S Sv - - - POP_SEG D64
0faa NP - - - - RSM F=586
0fab MR Ev Gv - - BTS LOCK EFL=u--u-uum
0fac MRI Ev Gv Ib - SHRD EFL=u--mmumm
0fad MRC Ev Gv Rb - SHRD EFL=u--mmumm
0faf RM Gv Ev - - IMUL EFL=m--uuuum
0fb0 MR Eb Gb - - CMPXCHG LOCK SZ8 F=486 EFL=m--mmmmm
0fb1 MR Ev Gv - - CMPXCHG LOCK F=486 EFL=m--mmmmm
0fb2/m RM Gv Mp - - LSS
0fb3 MR Ev Gv - - BTR LOCK EFL=u--u-uum
0fb4/m RM Gv Mp - - LFS
0fb5/m RM Gv Mp - - LGS
0fb6 RM Gv Eb - - MOVZX ENC_SEPSZ
0fb7 RM Gv Ew - - MOVZX ENC_SEPSZ
F3.0fb8 RM Gv Ev - - POPCNT U66 F=POPCNT EFL=0--0m000
0fb9 RM Gv Ev - - UD1
0fba/4 MI Ev Ib - - BT EFL=u--u-uum
0fba/5 MI Ev Ib - - BTS LOCK EFL=u--u-uum
0fba/6 MI Ev Ib - - BTR LOCK EFL=u--u-uum
0fba/7 MI Ev Ib - - BTC LOCK EFL=u--u-uum
0fbb MR Ev Gv - - BTC LOCK EFL=u--u-uum
*0fbc RM Gv Ev - - BSF EFL=u--umuuu
F3.0fbc RM Gv Ev - - TZCNT U66 F=BMI1 EFL=u--umuum
*0fbd RM Gv Ev - - BSR EFL=u--umuuu
F3.0fbd RM Gv Ev - - LZCNT U66 F=LZCNT EFL=u--umuum
0fbe RM Gv Eb - - MOVSX ENC_SEPSZ
0fbf RM Gv Ew - - MOVSX ENC_SEPSZ
0fc0 MR Eb Gb - - XADD LOCK SZ8 F=486 EFL=m--mmmmm
0fc1 MR Ev Gv - - XADD LOCK F=486 EFL=m--mmmmm
NP.0fc3/m MR My Gy - - MOVNTI F=SSE2
0fc7/1m M M - - - CMPXCHGD+w LOCK I66 F=586 EFL=----m---
0fc8+ O Rv - - - BSWAP F=486
0fff RM Gv Ev - - UD0
#
NFx.0f38f0/m RM Gv Mv - - MOVBE F=MOVBE
F2.0f38f0 RM Gd Eb - - CRC32 SZ8 F=SSE42
NFx.0f38f1/m MR Mv Gv - - MOVBE F=MOVBE
F2.0f38f1 RM Gd Ev - - CRC32 U66 F=SSE42
#
# MMX
NP.0f2a RM Vq Qq - - MMX_CVTPI2PS F=SSE2
66.0f2a RM Vdq Qq - - MMX_CVTPI2PD F=SSE2
NP.0f2c RM Pq Wq - - MMX_CVTTPS2PI F=SSE2
66.0f2c RM Pq Wdq - - MMX_CVTTPD2PI F=SSE2
NP.0f2d RM Pq Wq - - MMX_CVTPS2PI F=SSE2
66.0f2d RM Pq Wdq - - MMX_CVTPD2PI F=SSE2
NP.0f60 RM Pq Qd - - MMX_PUNPCKLBW F=MMX
NP.0f61 RM Pq Qd - - MMX_PUNPCKLWD F=MMX
NP.0f62 RM Pq Qd - - MMX_PUNPCKLDQ F=MMX
NP.0f63 RM Pq Qq - - MMX_PACKSSWB F=MMX
NP.0f64 RM Pq Qq - - MMX_PCMPGTB F=MMX
NP.0f65 RM Pq Qq - - MMX_PCMPGTW F=MMX
NP.0f66 RM Pq Qq - - MMX_PCMPGTD F=MMX
NP.0f67 RM Pq Qq - - MMX_PACKUSWB F=MMX
NP.0f68 RM Pq Qq - - MMX_PUNPCKHBW F=MMX
NP.0f69 RM Pq Qq - - MMX_PUNPCKHWD F=MMX
NP.0f6a RM Pq Qq - - MMX_PUNPCKHDQ F=MMX
NP.0f6b RM Pq Qq - - MMX_PACKSSDW F=MMX
NP.W0.0f6e RM Pq Ey - - MMX_MOVD_G2M F=MMX ENC_NOSZ
NP.W1.0f6e RM Pq Ey - - MMX_MOVQ_G2M F=MMX ENC_NOSZ
NP.0f6f RM Pq Qq - - MMX_MOVQ F=MMX
NP.0f70 RMI Pq Qq Ib - MMX_PSHUFW F=SSE
NP.0f71/2r MI Nq Ib - - MMX_PSRLW F=MMX
NP.0f71/4r MI Nq Ib - - MMX_PSRAW F=MMX
NP.0f71/6r MI Nq Ib - - MMX_PSLLW F=MMX
NP.0f72/2r MI Nq Ib - - MMX_PSRLD F=MMX
NP.0f72/4r MI Nq Ib - - MMX_PSRAD F=MMX
NP.0f72/6r MI Nq Ib - - MMX_PSLLD F=MMX
NP.0f73/2r MI Nq Ib - - MMX_PSRLQ F=MMX
NP.0f73/6r MI Nq Ib - - MMX_PSLLQ F=MMX
NP.0f74 RM Pq Qq - - MMX_PCMPEQB F=MMX
NP.0f75 RM Pq Qq - - MMX_PCMPEQW F=MMX
NP.0f76 RM Pq Qq - - MMX_PCMPEQD F=MMX
NP.0f77 NP - - - - MMX_EMMS F=MMX
NP.W0.0f7e MR Ey Py - - MMX_MOVD_M2G F=MMX ENC_NOSZ
NP.W1.0f7e MR Ey Py - - MMX_MOVQ_M2G F=MMX ENC_NOSZ
NP.0f7f MR Qq Pq - - MMX_MOVQ F=MMX
NP.0fc4 RMI Pq Ew Ib - MMX_PINSRW F=SSE ENC_NOSZ
NP.0fc5/r RMI Gy Nq Ib - MMX_PEXTRW D64 F=SSE
NP.0fd1 RM Pq Qq - - MMX_PSRLW F=MMX
NP.0fd2 RM Pq Qq - - MMX_PSRLD F=MMX
NP.0fd3 RM Pq Qq - - MMX_PSRLQ F=MMX
NP.0fd4 RM Pq Qq - - MMX_PADDQ F=MMX
NP.0fd5 RM Pq Qq - - MMX_PMULLW F=MMX
F2.0fd6/r RM Pq Uq - - MMX_MOVDQ2Q F=SSE
F3.0fd6/r RM Vdq Nq - - MMX_MOVQ2DQ F=SSE
NP.0fd7/r RM Gv Nq - - MMX_PMOVMSKB D64 F=SSE
NP.0fd8 RM Pq Qq - - MMX_PSUBUSB F=MMX
NP.0fd9 RM Pq Qq - - MMX_PSUBUSW F=MMX
NP.0fda RM Pq Qq - - MMX_PMINUB F=SSE
NP.0fdb RM Pq Qq - - MMX_PAND F=MMX
NP.0fdc RM Pq Qq - - MMX_PADDUSB F=MMX
NP.0fdd RM Pq Qq - - MMX_PADDUSW F=MMX
NP.0fde RM Pq Qq - - MMX_PMAXUB F=SSE
NP.0fdf RM Pq Qq - - MMX_PANDN F=MMX
NP.0fe0 RM Pq Qq - - MMX_PAVGB F=SSE
NP.0fe1 RM Pq Qq - - MMX_PSRAW F=MMX
NP.0fe2 RM Pq Qq - - MMX_PSRAD F=MMX
NP.0fe3 RM Pq Qq - - MMX_PAVGW F=SSE
NP.0fe4 RM Pq Qq - - MMX_PMULHUW F=SSE
NP.0fe5 RM Pq Qq - - MMX_PMULHW F=MMX
NP.0fe7/m MR Mq Pq - - MMX_MOVNTQ F=SSE
NP.0fe8 RM Pq Qq - - MMX_PSUBSB F=MMX
NP.0fe9 RM Pq Qq - - MMX_PSUBSW F=MMX
NP.0feb RM Pq Qq - - MMX_POR F=MMX
NP.0fec RM Pq Qq - - MMX_PADDSB F=MMX
NP.0fea RM Pq Qq - - MMX_PMINSW F=SSE
NP.0fee RM Pq Qq - - MMX_PMAXSW F=SSE
NP.0fed RM Pq Qq - - MMX_PADDSW F=MMX
NP.0fef RM Pq Qq - - MMX_PXOR F=MMX
NP.0ff1 RM Pq Qq - - MMX_PSLLW F=MMX
NP.0ff2 RM Pq Qq - - MMX_PSLLD F=MMX
NP.0ff3 RM Pq Qq - - MMX_PSLLQ F=MMX
NP.0ff4 RM Pq Qq - - MMX_PMULUDQ F=MMX
NP.0ff5 RM Pq Qq - - MMX_PMADDWD F=MMX
NP.0ff6 RM Pq Qq - - MMX_PSADBW F=SSE
NP.0ff7/r RM Pq Nq - - MMX_MASKMOVQ+as F=SSE
NP.0ff8 RM Pq Qq - - MMX_PSUBB F=MMX
NP.0ff9 RM Pq Qq - - MMX_PSUBW F=MMX
NP.0ffa RM Pq Qq - - MMX_PSUBD F=MMX
NP.0ffb RM Pq Qq - - MMX_PSUBQ F=MMX
NP.0ffc RM Pq Qq - - MMX_PADDB F=MMX
NP.0ffd RM Pq Qq - - MMX_PADDW F=MMX
NP.0ffe RM Pq Qq - - MMX_PADDD F=MMX
NP.0f3800 RM Pq Qq - - MMX_PSHUFB F=SSSE3
NP.0f3801 RM Pq Qq - - MMX_PHADDW F=SSSE3
NP.0f3802 RM Pq Qq - - MMX_PHADDD F=SSSE3
NP.0f3803 RM Pq Qq - - MMX_PHADDSW F=SSSE3
NP.0f3804 RM Pq Qq - - MMX_PMADDUBSW F=SSSE3
NP.0f3805 RM Pq Qq - - MMX_PHSUBW F=SSSE3
NP.0f3806 RM Pq Qq - - MMX_PHSUBD F=SSSE3
NP.0f3807 RM Pq Qq - - MMX_PHSUBSW F=SSSE3
NP.0f3808 RM Pq Qq - - MMX_PSIGNB F=SSSE3
NP.0f3809 RM Pq Qq - - MMX_PSIGNW F=SSSE3
NP.0f380a RM Pq Qq - - MMX_PSIGND F=SSSE3
NP.0f380b RM Pq Qq - - MMX_PMULHRSW F=SSSE3
NP.0f381c RM Pq Qq - - MMX_PABSB F=SSSE3
NP.0f381d RM Pq Qq - - MMX_PABSW F=SSSE3
NP.0f381e RM Pq Qq - - MMX_PABSD F=SSSE3
NP.0f3a0f RMI Pq Qq Ib - MMX_PALIGNR F=SSSE3
#
# SSE
NP.0f10 RM Vps Wps - - SSE_MOVUPS F=SSE
66.0f10 RM Vpd Wpd - - SSE_MOVUPD F=SSE2
# MOVSS/MOVSD reg,mem set the full XMM register
F3.0f10 RM Vx Wss - - SSE_MOVSS F=SSE
F2.0f10 RM Vx Wsd - - SSE_MOVSD F=SSE2
NP.0f11 MR Wps Vps - - SSE_MOVUPS F=SSE
66.0f11 MR Wpd Vpd - - SSE_MOVUPD F=SSE2
F3.0f11 MR Wss Vss - - SSE_MOVSS F=SSE
F2.0f11 MR Wsd Vsd - - SSE_MOVSD F=SSE2
NP.0f12/m RM Vx Mq - - SSE_MOVLPS F=SSE
NP.0f12/r RM Vx Ux - - SSE_MOVHLPS F=SSE
66.0f12/m RM Vx Mq - - SSE_MOVLPD F=SSE2
F3.0f12 RM Vx Wx - - SSE_MOVSLDUP F=SSE3
F2.0f12 RM Vx Wq - - SSE_MOVDDUP F=SSE3
NP.0f13/m MR Mq Vq - - SSE_MOVLPS F=SSE
66.0f13/m MR Mq Vq - - SSE_MOVLPD F=SSE2
NP.0f14 RM Vps Wps - - SSE_UNPCKLPS F=SSE
66.0f14 RM Vpd Wpd - - SSE_UNPCKLPD F=SSE2
NP.0f15 RM Vps Wps - - SSE_UNPCKHPS F=SSE
66.0f15 RM Vpd Wpd - - SSE_UNPCKHPD F=SSE2
NP.0f16/m RM Vx Mq - - SSE_MOVHPS F=SSE
NP.0f16/r RM Vx Uq - - SSE_MOVLHPS F=SSE
66.0f16/m RM Vdq Mq - - SSE_MOVHPD F=SSE2
F3.0f16 RM Vx Wx - - SSE_MOVSHDUP F=SSE3
NP.0f17/m MR Mq Vx - - SSE_MOVHPS F=SSE
66.0f17/m MR Mq Vx - - SSE_MOVHPD F=SSE2
NP.0f28 RM Vps Wps - - SSE_MOVAPS F=SSE
66.0f28 RM Vpd Wpd - - SSE_MOVAPD F=SSE2
NP.0f29 MR Wps Vps - - SSE_MOVAPS F=SSE
66.0f29 MR Wpd Vpd - - SSE_MOVAPD F=SSE2
F3.0f2a RM Vss Ey - - SSE_CVTSI2SS F=SSE
F2.0f2a RM Vsd Ey - - SSE_CVTSI2SD F=SSE2
NP.0f2b/m MR Mps Vps - - SSE_MOVNTPS F=SSE
66.0f2b/m MR Mpd Vpd - - SSE_MOVNTPD F=SSE2
F3.0f2b/m MR Mss Vss - - SSE_MOVNTSS F=SSE ONLYAMD
F2.0f2b/m MR Msd Vsd - - SSE_MOVNTSD F=SSE2 ONLYAMD
F3.0f2c RM Gy Wss - - SSE_CVTTSS2SI F=SSE
F2.0f2c RM Gy Wsd - - SSE_CVTTSD2SI F=SSE2
F3.0f2d RM Gy Wss - - SSE_CVTSS2SI F=SSE
F2.0f2d RM Gy Wsd - - SSE_CVTSD2SI F=SSE2
NP.0f2e RM Vss Wss - - SSE_UCOMISS F=SSE EFL=0--0m0mm
66.0f2e RM Vsd Wsd - - SSE_UCOMISD F=SSE2 EFL=0--0m0mm
NP.0f2f RM Vss Wss - - SSE_COMISS F=SSE EFL=0--0m0mm
66.0f2f RM Vsd Wsd - - SSE_COMISD F=SSE2 EFL=0--0m0mm
NP.0f50/r RM Gy Udq - - SSE_MOVMSKPS D64 F=SSE
66.0f50/r RM Gy Udq - - SSE_MOVMSKPD D64 F=SSE2
NP.0f51 RM Vps Wps - - SSE_SQRTPS F=SSE
66.0f51 RM Vpd Wpd - - SSE_SQRTPD F=SSE2
F3.0f51 RM Vss Wss - - SSE_SQRTSS F=SSE
F2.0f51 RM Vsd Wsd - - SSE_SQRTSD F=SSE2
NP.0f52 RM Vps Wps - - SSE_RSQRTPS F=SSE
F3.0f52 RM Vss Wss - - SSE_RSQRTSS F=SSE
NP.0f53 RM Vps Wps - - SSE_RCPPS F=SSE
F3.0f53 RM Vss Wss - - SSE_RCPSS F=SSE
NP.0f54 RM Vps Wps - - SSE_ANDPS F=SSE
66.0f54 RM Vpd Wpd - - SSE_ANDPD F=SSE2
NP.0f55 RM Vps Wps - - SSE_ANDNPS F=SSE
66.0f55 RM Vpd Wpd - - SSE_ANDNPD F=SSE2
NP.0f56 RM Vps Wps - - SSE_ORPS F=SSE
66.0f56 RM Vpd Wpd - - SSE_ORPD F=SSE2
NP.0f57 RM Vps Wps - - SSE_XORPS F=SSE
66.0f57 RM Vpd Wpd - - SSE_XORPD F=SSE2
NP.0f58 RM Vps Wps - - SSE_ADDPS F=SSE
66.0f58 RM Vpd Wpd - - SSE_ADDPD F=SSE2
F3.0f58 RM Vss Wss - - SSE_ADDSS F=SSE
F2.0f58 RM Vsd Wsd - - SSE_ADDSD F=SSE2
NP.0f59 RM Vps Wps - - SSE_MULPS F=SSE
66.0f59 RM Vpd Wpd - - SSE_MULPD F=SSE2
F3.0f59 RM Vss Wss - - SSE_MULSS F=SSE
F2.0f59 RM Vsd Wsd - - SSE_MULSD F=SSE2
NP.0f5a RM Vpd Wq - - SSE_CVTPS2PD F=SSE2
66.0f5a RM Vps Wpd - - SSE_CVTPD2PS F=SSE2
F3.0f5a RM Vsd Wss - - SSE_CVTSS2SD F=SSE2
F2.0f5a RM Vss Wsd - - SSE_CVTSD2SS F=SSE2
NP.0f5b RM Vps Wdq - - SSE_CVTDQ2PS F=SSE2
66.0f5b RM Vdq Wps - - SSE_CVTPS2DQ F=SSE2
F3.0f5b RM Vdq Wps - - SSE_CVTTPS2DQ F=SSE2
NP.0f5c RM Vps Wps - - SSE_SUBPS F=SSE
66.0f5c RM Vpd Wpd - - SSE_SUBPD F=SSE2
F3.0f5c RM Vss Wss - - SSE_SUBSS F=SSE
F2.0f5c RM Vsd Wsd - - SSE_SUBSD F=SSE2
NP.0f5d RM Vps Wps - - SSE_MINPS F=SSE
66.0f5d RM Vpd Wpd - - SSE_MINPD F=SSE2
F3.0f5d RM Vss Wss - - SSE_MINSS F=SSE
F2.0f5d RM Vsd Wsd - - SSE_MINSD F=SSE2
NP.0f5e RM Vps Wps - - SSE_DIVPS F=SSE
66.0f5e RM Vpd Wpd - - SSE_DIVPD F=SSE2
F3.0f5e RM Vss Wss - - SSE_DIVSS F=SSE
F2.0f5e RM Vsd Wsd - - SSE_DIVSD F=SSE2
NP.0f5f RM Vps Wps - - SSE_MAXPS F=SSE
66.0f5f RM Vpd Wpd - - SSE_MAXPD F=SSE2
F3.0f5f RM Vss Wss - - SSE_MAXSS F=SSE
F2.0f5f RM Vsd Wsd - - SSE_MAXSD F=SSE2
66.0f60 RM Vx Wx - - SSE_PUNPCKLBW F=SSE2
66.0f61 RM Vx Wx - - SSE_PUNPCKLWD F=SSE2
66.0f62 RM Vx Wx - - SSE_PUNPCKLDQ F=SSE2
66.0f63 RM Vx Wx - - SSE_PACKSSWB F=SSE2
66.0f64 RM Vx Wx - - SSE_PCMPGTB F=SSE2
66.0f65 RM Vx Wx - - SSE_PCMPGTW F=SSE2
66.0f66 RM Vx Wx - - SSE_PCMPGTD F=SSE2
66.0f67 RM Vx Wx - - SSE_PACKUSWB F=SSE2
66.0f68 RM Vx Wx - - SSE_PUNPCKHBW F=SSE2
66.0f69 RM Vx Wx - - SSE_PUNPCKHWD F=SSE2
66.0f6a RM Vx Wx - - SSE_PUNPCKHDQ F=SSE2
66.0f6b RM Vx Wx - - SSE_PACKSSDW F=SSE2
66.0f6c RM Vx Wx - - SSE_PUNPCKLQDQ F=SSE2
66.0f6d RM Vx Wx - - SSE_PUNPCKHQDQ F=SSE2
66.W0.0f6e RM Vx Ed - - SSE_MOVD_G2X F=SSE2 ENC_NOSZ
66.W1.0f6e RM Vx Eq - - SSE_MOVQ_G2X F=SSE2 ENC_NOSZ
66.0f6f RM Vx Wx - - SSE_MOVDQA F=SSE2
F3.0f6f RM Vx Wx - - SSE_MOVDQU F=SSE2
66.0f70 RMI Vx Wx Ib - SSE_PSHUFD F=SSE2
F3.0f70 RMI Vx Wx Ib - SSE_PSHUFHW F=SSE2
F2.0f70 RMI Vx Wx Ib - SSE_PSHUFLW F=SSE2
66.0f71/2r MI Ux Ib - - SSE_PSRLW F=SSE2
66.0f71/4r MI Ux Ib - - SSE_PSRAW F=SSE2
66.0f71/6r MI Ux Ib - - SSE_PSLLW F=SSE2
66.0f72/2r MI Ux Ib - - SSE_PSRLD F=SSE2
66.0f72/4r MI Ux Ib - - SSE_PSRAD F=SSE2
66.0f72/6r MI Ux Ib - - SSE_PSLLD F=SSE2
66.0f73/2r MI Ux Ib - - SSE_PSRLQ F=SSE2
66.0f73/3r MI Ux Ib - - SSE_PSRLDQ F=SSE2
66.0f73/6r MI Ux Ib - - SSE_PSLLQ F=SSE2
66.0f73/7r MI Ux Ib - - SSE_PSLLDQ F=SSE2
66.0f74 RM Vx Wx - - SSE_PCMPEQB F=SSE2
66.0f75 RM Vx Wx - - SSE_PCMPEQW F=SSE2
66.0f76 RM Vx Wx - - SSE_PCMPEQD F=SSE2
# EXTRQ/INSERTQ immediate size handled in code.
66.0f78/0r MI Ux Iw - - SSE_EXTRQ F=SSE4A ONLYAMD
F2.0f78/r RMI Vx Ux Iw - SSE_INSERTQ F=SSE4A ONLYAMD
66.0f79/r RM Vx Ux - - SSE_EXTRQ F=SSE4A ONLYAMD
F2.0f79/r RM Vx Ux - - SSE_INSERTQ F=SSE4A ONLYAMD
66.0f7c RM Vx Wx - - SSE_HADDPD F=SSE3
F2.0f7c RM Vx Wx - - SSE_HADDPS F=SSE3
66.0f7d RM Vx Wx - - SSE_HSUBPD F=SSE3
F2.0f7d RM Vx Wx - - SSE_HSUBPS F=SSE3
66.W0.0f7e MR Ey Vy - - SSE_MOVD_X2G F=SSE2 ENC_NOSZ
66.W1.0f7e MR Ey Vy - - SSE_MOVQ_X2G F=SSE2 ENC_NOSZ
F3.0f7e RM Vx Wq - - SSE_MOVQ F=SSE2
66.0f7f MR Wx Vx - - SSE_MOVDQA F=SSE2
F3.0f7f MR Wx Vx - - SSE_MOVDQU F=SSE2
NP.0fae/0m M M - - - FXSAVE+w F=FXSR
NP.0fae/1m M M - - - FXRSTOR+w F=FXSR
NP.0fae/2m M Md - - - LDMXCSR F=SSE
NP.0fae/3m M Md - - - STMXCSR F=SSE
NP.0faee8+ NP - - - - LFENCE F=SSE2
NP.0faef0+ NP - - - - MFENCE F=SSE2
NP.0faef8+ NP - - - - SFENCE F=SSE
NP.0fc2 RMI Vps Wps Ib - SSE_CMPPS F=SSE
66.0fc2 RMI Vpd Wpd Ib - SSE_CMPPD F=SSE2
F3.0fc2 RMI Vss Wss Ib - SSE_CMPSS F=SSE
F2.0fc2 RMI Vsd Wsd Ib - SSE_CMPSD F=SSE2
66.0fc4 RMI Vx Ew Ib - SSE_PINSRW F=SSE2 ENC_NOSZ
66.0fc5/r RMI Gy Udq Ib - SSE_PEXTRW D64 F=SSE2 ENC_NOSZ
NP.0fc6 RMI Vps Wps Ib - SSE_SHUFPS F=SSE
66.0fc6 RMI Vpd Wpd Ib - SSE_SHUFPD F=SSE2
66.0fd0 RM Vps Wps - - SSE_ADDSUBPD F=SSE3
F2.0fd0 RM Vpd Wpd - - SSE_ADDSUBPS F=SSE3
66.0fd1 RM Vx Wx - - SSE_PSRLW F=SSE2
66.0fd2 RM Vx Wx - - SSE_PSRLD F=SSE2
66.0fd3 RM Vx Wx - - SSE_PSRLQ F=SSE2
66.0fd4 RM Vx Wx - - SSE_PADDQ F=SSE2
66.0fd5 RM Vx Wx - - SSE_PMULLW F=SSE2
# This is tricky, MOVQ to mem writes 64 bits, MOVQ to reg writes 128 bits
66.0fd6 MR Wq Vq - - SSE_MOVQ F=SSE2
66.0fd7/r RM Gy Udq - - SSE_PMOVMSKB D64 F=SSE2
66.0fd8 RM Vx Wx - - SSE_PSUBUSB F=SSE2
66.0fd9 RM Vx Wx - - SSE_PSUBUSW F=SSE2
66.0fda RM Vx Wx - - SSE_PMINUB F=SSE2
66.0fdb RM Vx Wx - - SSE_PAND F=SSE2
66.0fdc RM Vx Wx - - SSE_PADDUSB F=SSE2
66.0fdd RM Vx Wx - - SSE_PADDUSW F=SSE2
66.0fde RM Vx Wx - - SSE_PMAXUB F=SSE2
66.0fdf RM Vx Wx - - SSE_PANDN F=SSE2
66.0fe0 RM Vx Wx - - SSE_PAVGB F=SSE2
66.0fe1 RM Vx Wx - - SSE_PSRAW F=SSE2
66.0fe2 RM Vx Wx - - SSE_PSRAD F=SSE2
66.0fe3 RM Vx Wx - - SSE_PAVGW F=SSE2
66.0fe4 RM Vx Wx - - SSE_PMULHUW F=SSE2
66.0fe5 RM Vx Wx - - SSE_PMULHW F=SSE2
66.0fe6 RM Vx Wpd - - SSE_CVTTPD2DQ F=SSE2
F3.0fe6 RM Vpd Wq - - SSE_CVTDQ2PD F=SSE2
F2.0fe6 RM Vx Wpd - - SSE_CVTPD2DQ F=SSE2
66.0fe7/m MR Mx Vx - - SSE_MOVNTDQ F=SSE2
66.0fe8 RM Vx Wx - - SSE_PSUBSB F=SSE2
66.0fe9 RM Vx Wx - - SSE_PSUBSW F=SSE2
66.0feb RM Vx Wx - - SSE_POR F=SSE2
66.0fec RM Vx Wx - - SSE_PADDSB F=SSE2
66.0fea RM Vx Wx - - SSE_PMINSW F=SSE2
66.0fee RM Vx Wx - - SSE_PMAXSW F=SSE2
66.0fed RM Vx Wx - - SSE_PADDSW F=SSE2
66.0fef RM Vx Wx - - SSE_PXOR F=SSE2
F2.0ff0/m RM Vx Mx - - SSE_LDDQU F=SSE3
66.0ff1 RM Vx Wx - - SSE_PSLLW F=SSE2
66.0ff2 RM Vx Wx - - SSE_PSLLD F=SSE2
66.0ff3 RM Vx Wx - - SSE_PSLLQ F=SSE2
66.0ff4 RM Vx Wx - - SSE_PMULUDQ F=SSE2
66.0ff5 RM Vx Wx - - SSE_PMADDWD F=SSE2
66.0ff6 RM Vx Wx - - SSE_PSADBW F=SSE2
66.0ff7/r RM Vx Ux - - SSE_MASKMOVDQU+as F=SSE2
66.0ff8 RM Vx Wx - - SSE_PSUBB F=SSE2
66.0ff9 RM Vx Wx - - SSE_PSUBW F=SSE2
66.0ffa RM Vx Wx - - SSE_PSUBD F=SSE2
66.0ffb RM Vx Wx - - SSE_PSUBQ F=SSE2
66.0ffc RM Vx Wx - - SSE_PADDB F=SSE2
66.0ffd RM Vx Wx - - SSE_PADDW F=SSE2
66.0ffe RM Vx Wx - - SSE_PADDD F=SSE2
#
66.0f3800 RM Vx Wx - - SSE_PSHUFB F=SSSE3
66.0f3801 RM Vx Wx - - SSE_PHADDW F=SSSE3
66.0f3802 RM Vx Wx - - SSE_PHADDD F=SSSE3
66.0f3803 RM Vx Wx - - SSE_PHADDSW F=SSSE3
66.0f3804 RM Vx Wx - - SSE_PMADDUBSW F=SSSE3
66.0f3805 RM Vx Wx - - SSE_PHSUBW F=SSSE3
66.0f3806 RM Vx Wx - - SSE_PHSUBD F=SSSE3
66.0f3807 RM Vx Wx - - SSE_PHSUBSW F=SSSE3
66.0f3808 RM Vx Wx - - SSE_PSIGNB F=SSSE3
66.0f3809 RM Vx Wx - - SSE_PSIGNW F=SSSE3
66.0f380a RM Vx Wx - - SSE_PSIGND F=SSSE3
66.0f380b RM Vx Wx - - SSE_PMULHRSW F=SSSE3
66.0f3810 RM Vdq Wdq - - SSE_PBLENDVB F=SSE41
66.0f3814 RMA Vdq Wdq Hdq - SSE_BLENDVPS F=SSE41
66.0f3815 RMA Vdq Wdq Hdq - SSE_BLENDVPD F=SSE41
66.0f3817 RM Vx Wx - - SSE_PTEST F=SSE41 EFL=0--0m00m
66.0f381c RM Vx Wx - - SSE_PABSB F=SSSE3
66.0f381d RM Vx Wx - - SSE_PABSW F=SSSE3
66.0f381e RM Vx Wx - - SSE_PABSD F=SSSE3
66.0f3820 RM Vx Wh - - SSE_PMOVSXBW F=SSE41
66.0f3821 RM Vx Wf - - SSE_PMOVSXBD F=SSE41
66.0f3822 RM Vx We - - SSE_PMOVSXBQ F=SSE41
66.0f3823 RM Vx Wh - - SSE_PMOVSXWD F=SSE41
66.0f3824 RM Vx Wf - - SSE_PMOVSXWQ F=SSE41
66.0f3825 RM Vx Wh - - SSE_PMOVSXDQ F=SSE41
66.0f3828 RM Vx Wx - - SSE_PMULDQ F=SSE41
66.0f3829 RM Vx Wx - - SSE_PCMPEQQ F=SSE41
66.0f382a/m RM Vx Mx - - SSE_MOVNTDQA F=SSE41
66.0f382b RM Vx Wx - - SSE_PACKUSDW F=SSE41
66.0f3830 RM Vx Wh - - SSE_PMOVZXBW F=SSE41
66.0f3831 RM Vx Wf - - SSE_PMOVZXBD F=SSE41
66.0f3832 RM Vx We - - SSE_PMOVZXBQ F=SSE41
66.0f3833 RM Vx Wh - - SSE_PMOVZXWD F=SSE41
66.0f3834 RM Vx Wf - - SSE_PMOVZXWQ F=SSE41
66.0f3835 RM Vx Wh - - SSE_PMOVZXDQ F=SSE41
66.0f3837 RM Vx Wx - - SSE_PCMPGTQ F=SSE41
66.0f3838 RM Vx Wx - - SSE_PMINSB F=SSE41
66.0f3839 RM Vx Wx - - SSE_PMINSD F=SSE41
66.0f383a RM Vx Wx - - SSE_PMINUW F=SSE41
66.0f383b RM Vx Wx - - SSE_PMINUD F=SSE41
66.0f383c RM Vx Wx - - SSE_PMAXSB F=SSE41
66.0f383d RM Vx Wx - - SSE_PMAXSD F=SSE41
66.0f383e RM Vx Wx - - SSE_PMAXUW F=SSE41
66.0f383f RM Vx Wx - - SSE_PMAXUD F=SSE41
66.0f3840 RM Vx Wx - - SSE_PMULLD F=SSE41
66.0f3841 RM Vx Wx - - SSE_PHMINPOSUW F=SSE41
# TODO: GP operand has address size
66.0f38f8/m RM Gy Moq - - MOVDIR64B D64 F=MOVDIR64B
NP.0f38f9/m MR My Gy - - MOVDIRI F=MOVDIRI
#
66.0f3a08 RMI Vps Wps Ib - SSE_ROUNDPS F=SSE41
66.0f3a09 RMI Vpd Wpd Ib - SSE_ROUNDPD F=SSE41
66.0f3a0a RMI Vss Wss Ib - SSE_ROUNDSS F=SSE41
66.0f3a0b RMI Vsd Wsd Ib - SSE_ROUNDSD F=SSE41
66.0f3a0c RMI Vps Wps Ib - SSE_BLENDPS F=SSE41
66.0f3a0d RMI Vpd Wpd Ib - SSE_BLENDPD F=SSE41
66.0f3a0e RMI Vx Wx Ib - SSE_PBLENDW F=SSE41
66.0f3a0f RMI Vx Wx Ib - SSE_PALIGNR F=SSSE3
66.0f3a14/m MRI Mb Vx Ib - SSE_PEXTRB F=SSE41
66.0f3a14/r MRI Rd Vx Ib - SSE_PEXTRB F=SSE41 ENC_NOSZ
66.0f3a15/m MRI Mw Vx Ib - SSE_PEXTRW F=SSE41
66.0f3a15/r MRI Rd Vx Ib - SSE_PEXTRW F=SSE41 ENC_NOSZ
66.W0.0f3a16 MRI Ed Vx Ib - SSE_PEXTRD F=SSE41 ENC_NOSZ
66.W1.0f3a16 MRI Eq Vx Ib - SSE_PEXTRQ F=SSE41 ENC_NOSZ
66.0f3a17 MRI Ed Vx Ib - SSE_EXTRACTPS F=SSE41
66.0f3a20 RMI Vx Eb Ib - SSE_PINSRB F=SSE41
66.0f3a21 RMI Vps Wss Ib - SSE_INSERTPS F=SSE41
66.W0.0f3a22 RMI Vx Ed Ib - SSE_PINSRD F=SSE41 ENC_NOSZ
66.W1.0f3a22 RMI Vx Eq Ib - SSE_PINSRQ F=SSE41 ENC_NOSZ
66.0f3a40 RMI Vps Wps Ib - SSE_DPPS F=SSE41
66.0f3a41 RMI Vpd Wpd Ib - SSE_DPPD F=SSE41
66.0f3a42 RMI Vx Wx Ib - SSE_MPSADBW F=SSE41
66.0f3a44 RMI Vdq Wdq Ib - SSE_PCLMULQDQ F=PCLMULQDQ
66.0f3a60 RMI Vdq Wdq Ib - SSE_PCMPESTRM F=SSE42 EFL=m--mm00m
66.0f3a61 RMI Vdq Wdq Ib - SSE_PCMPESTRI F=SSE42 EFL=m--mm00m
66.0f3a62 RMI Vdq Wdq Ib - SSE_PCMPISTRM F=SSE42 EFL=m--mm00m
66.0f3a63 RMI Vdq Wdq Ib - SSE_PCMPISTRI F=SSE42 EFL=m--mm00m
#
66.0f38db RM Vdq Wdq - - AESIMC F=AESNI
66.0f38dc RM Vdq Wdq - - AESENC F=AESNI
66.0f38dd RM Vdq Wdq - - AESENCLAST F=AESNI
66.0f38de RM Vdq Wdq - - AESDEC F=AESNI
66.0f38df RM Vdq Wdq - - AESDECLAST F=AESNI
66.0f3adf RMI Vdq Wdq Ib - AESKEYGENASSIST F=AESNI
VEX.66.L0.0f38db RM Vdq Wdq - - VAESIMC F=AESNI,AVX
# 256-bit encodings require VAES.
VEX.66.0f38dc RVM Vx Hx Wx - VAESENC F=AESNI,AVX
VEX.66.0f38dd RVM Vx Hx Wx - VAESENCLAST F=AESNI,AVX
VEX.66.0f38de RVM Vx Hx Wx - VAESDEC F=AESNI,AVX
VEX.66.0f38df RVM Vx Hx Wx - VAESDECLAST F=AESNI,AVX
VEX.66.L0.0f3adf RMI Vdq Wdq Ib - VAESKEYGENASSIST F=AESNI,AVX
#
# AVX
VEX.NP.0f10 RM Vps Wps - - VMOVUPS F=AVX
VEX.66.0f10 RM Vpd Wpd - - VMOVUPD F=AVX
VEX.F3.LIG.0f10/m RM Vdq Mss - - VMOVSS F=AVX
VEX.F3.LIG.0f10/r RVM Vdq Hdq Uss - VMOVSS F=AVX
VEX.F2.LIG.0f10/m RM Vdq Msd - - VMOVSD F=AVX
VEX.F2.LIG.0f10/r RVM Vdq Hdq Usd - VMOVSD F=AVX
VEX.NP.0f11 MR Wps Vps - - VMOVUPS F=AVX