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Description
We've accumulated a number of issues that should be addressed with LLVM 20, so just opening this as a meta issue to track them all in one place:
- Compiler crash when targeting
mips64
when returningfp128
after calling a function returning{ i8, i128 }
llvm/llvm-project#96432 - [Hexagon][Docs] document the change in the default target llvm/llvm-project#125584
- Send patch to LLVM adding the muslabin32 target environment #2909
- [WebAssembly]
memcpy
does not result in no-op for zero-length slices #16360 -
behavior.vector.test.vector float operators
causes LLVM assertion failure onmips*-linux-*
#21051 - Remove "slow target" flag for
mips(el)-linux
targets in tests with LLVM 20 #21096 - Re-enable FastISel for MIPS O32 with LLVM 20 #21215
- Remove
s390x-linux-gnu
assembler workarounds with LLVM 20 #21329 - Remove the PowerPC soft float preprocessor workaround with LLVM 20 #21411
- Update our baseline and generic CPU models for WebAssembly #21818
- Remove the LoongArch
f16
lowering workaround with LLVM 20 #22003 - Enable red zone support for PowerPC after the LLVM 20 upgrade #23056
-
Lines 273 to 274 in a9c7714
-
Lines 2266 to 2273 in a9c7714
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Qualcomm Hexagon DSP32-bit and 64-bit LoongArch32-bit and 64-bit MIPS32-bit and 64-bit Power ISA64-bit IBM z/Architecture32-bit and 64-bit WebAssemblyThe LLVM backend outputs an LLVM IR Module.Observed behavior contradicts documented or intended behaviorSolving this issue will likely involve adding new logic or components to the codebase.This issue involves writing Zig code for the standard library.An issue with a third party project that Zig uses.Zig as a drop-in C compiler feature