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Missing x86 mnemonics and registers (self-hosted backend encoder) #19773

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Arnau478 opened this issue Apr 26, 2024 · 1 comment
Open

Missing x86 mnemonics and registers (self-hosted backend encoder) #19773

Arnau478 opened this issue Apr 26, 2024 · 1 comment
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arch-x86_64 64-bit x86 backend-self-hosted enhancement Solving this issue will likely involve adding new logic or components to the codebase.
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0.14.0

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@Arnau478
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Arnau478 commented Apr 26, 2024 •
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There are some assembly instruction mnemonics missing on the x86 backend, specially some CPL0 instructions like cli, sti, wrmsr, rdmsr, hlt, ltr, lidt, iretq, hlt... There are some registers missing too, namely the control registers (cr0, cr2, and so on).
@Arnau478 Arnau478 changed the title Implement every x86 mnemonic and register for the self-hosted backend encoder Missing x86 mnemonics and registers (self-hosted backend encoder) May 23, 2024
@Arnau478 Arnau478 mentioned this issue May 23, 2024
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@andrewrk andrewrk added enhancement Solving this issue will likely involve adding new logic or components to the codebase. arch-x86_64 64-bit x86 backend-self-hosted labels May 29, 2024
@andrewrk andrewrk added this to the 0.14.0 milestone May 29, 2024
@sfiedler0
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The int mnemonic is missing too…

It throws an interrupt (for example int $1) and can be really good for testing interrupt handlers in the kernel. So it would be nice if that could be implemented.

I just noticed, inb and outb (and as far as I can see all other ins and outs) are missing, so debug logging to UART does not work.

@sfiedler0 sfiedler0 mentioned this issue May 31, 2024
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@andrewrk andrewrk mentioned this issue Dec 17, 2024
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arch-x86_64 64-bit x86 backend-self-hosted enhancement Solving this issue will likely involve adding new logic or components to the codebase.
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Add missing assembly instructions to the x86 backend Arnau478/zig
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@andrewrk @Arnau478 @sfiedler0