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HEAD -- Version X.X.X
Version 2.1.3
(25 Aug, 2010)
Improvements:
* router kit builds correctly under Fedora 13
* GUI SCONE layout updated to display correctly under OpenJDK
* tutorial:
- switched to VLC from mplayer
(mplayer would crash when link broken/re-established)
- verify that the GUI scripts are run as root
* Java GUI automatically built if Java compiler exists on system
* simulation:
- don't list tests run in GUI mode as passing
- restrict GUI mode to a single test at a time
Bug fixes:
* cpci_reprogram.pl checks for root before reprogramming
* fix build issue if make install is run from top-level directory
Version 2.1.2
(6 Aug, 2010)
Improvements:
* Add parameter to disable registers on CPU DMA queues
* GUI SCONE:
- Makefiles to build class files
* Selftest:
- allow selftest to run when interfaces are down
- clean up output when DMA test fails
- increase time time for DMA transfer timeouts
* Gigabit MAC:
- new MAC provided by Erik Rubow at UCSD
- located in lib/verilog/contrib/ucsd/gig_eth_mac
- Note: NOT used by default. Must manually use this instead of the
default MAC core
Bug fixes:
* Fix libnet dependency to allow building on Fedora Core systems
(reported by Jonathan Ellithorpe <jdellit at stanford.edu>)
* Fix core dependency identification to prevent occassional problems
synthesizing/simulating with a clean tree
* cpci_reprogram.pl: report failure if dumpregs.sh/loadregs.sh fails
(reported by Berywn Hoyt <berwyn at brush.co.nz>)
* Simulation: don't run simulation if make_pkts.pl fails
* Fixed some instances of register defines files not being built when
installed from the .tar.gz
Version 2.1.1
(11 Jun, 2010)
Improvements:
* Increase DMA performance (bigger buffers to prevent stalls)
* SCONE builds correctly on more systems (removed dependence
on /usr/lib/libnet.a)
* Allow rkd to build under Ubuntu 10.04 (issue reported by gcarvajalb on
the forums)
Bug fixes:
* Some register writes were missed when doing back-to-back writes
(a buffer full signal was asserted too late)
Version 2.1.0
(28 May, 2010)
Improvements:
* Register system:
- project name included in the #define at the top of the C header file,
allowing the inclusion of multiple header files
- device ID info (version, name, desc) now specified in project.xml
- provide more information in headers at the top of generated files
- output bitmasks in C/Perl
* device_id module updated to include proj name, desc, and directory
* nf2_info utility updated and installed by default (reads the device ID
info from the active bitfile)
* Moved contributed code out of lib/verilog/core
* Added regression tests for the reference switch
* Packaging scripts:
- Verilog modules can be excluded
- support added for git repositories
* Selftest:
- uses new register system
- software verifies that the bitfile is downloaded before running the test
* Types added for CPCI registers with bitmasks
* Added functions to C common library:
- read device ID register
- verify that the correct bitfile is downloaded
* Kernel module:
- added basic ethtool support (Thanks to Kumar Sanghvi)
- added mii-tool support (Thanks to Kumar Sanghvi)
- support newer Linux kernels (net_device API deprecated)
(Thanks to Paul Rodman & Maciej Żenczykowski @ Google)
* DRAM related:
- DRAM block read/write test, DRAM queue test (1 queue), DRAM router
(8 queue) now released as full source code
- Several timing improvement to make the DRAM related modules faster
* Simulations:
- verify that the correct number of register reads is performed
- supports Xilinx ISim in addition to ModelSim and VCS
* DMA:
- added registers to nf2_dma and cpu_dma_queues
- cleaned up DMA code
- eliminated need for add_rm_hdr module
Bug fixes:
* numerous fixes to register system:
- incorrectly output of instance block addresses
- replace periods with underscores in identifier names
* cpci_download:
- should work correctly on Fedora systems
(Thanks to Paul Rodman)
* cleaned up logic in DMA -> reduction in timeout errors
Other changes:
* CPCI project renamed: CPCI_2.1 -> cpci
* CPCI PERL library updated: CPCI_21Lib.pm -> CPCI_Lib.pm
* Preparation for 10G system:
- Perl NF2 library renamed to NF
- nf2 replaced with nf in utility names (eg. nf_download)
- NetFPGA directory renamed to netfpga (instead of NF2)
Version 2.0.1 beta
(29 Sep, 2009)
Improvements:
* Modified packaging script to support core and contibuted verilog libraries
* Added regression tests to Reference Switch
* Released Reference Switch
Version 2.0 beta
(30 July, 2009)
Improvements:
* Generate CPCI Registers when building a Project
* JAVA GUI uses new Register System
* Reference NIC regression tests rewritten
* Support shared contants/types in XML
Version 2.0 alpha
(15 May, 2009)
Improvements:
* Register XML backend
* Added nf2_register_gen.pl to generate registers
* All scripts updated to create registers
* All reference designs updated to use project.xml file
* All library modules updated to use module xml files
* Updated nf2_download (allows for link status)
* DRAM Output FIFO
* Reference NIC regression tests rewritten
* Generic Table Registers (lib/verilog)
Bug fixes
* Rate limiter lockup condition fixed
Version 1.2.5-2 beta
(4 Feb, 2009)
Bug Fixes
* Fixed the regress.txt file located in NF2/projects
Version 1.2.5-1 beta
(22 Jan, 2009)
Bug fixes
* Replaced selftest bitfile to ensure it meets timing
Version 1.2.5 beta
(20 Jan, 2009)
Bug fixes
* MAC IO queues
- Disabled MAC truncation of packets for ethertypes < 46 (not all modules are short-packet safe)
* BRAM Output queues
- Fixed bug with register counter updates
Improvements:
* Driver
- DMA transfer errors include more debugging information
Version 1.2.4 beta
(11 Aug, 2008)
Minor new features and improvements:
* CPCI
- Corrected bug preventing programming of Virtex via JTAG immediately after power-on
Improvements:
* Updated location information in UCF files for CPCI reprogramming signals
(these are unused in all but the CPCI reprogrammer) -- eliminates warning
about location constraints for signal pins
Version 1.2.3 beta
(21 Jul, 2008)
Improvements:
* Updated the reference NIC and reference router regression tests
* Fixed the ucf files for projects (contributed from Jeff Shafer)
Version 1.2 beta revision 2
(10 Jul, 2008)
Minor improvment:
* CPCI
- Increased the DMA default timeout value
Version 1.2 beta
(08 Jul, 2008)
Major new features:
* Packaging
- RPM packages released to improve installation process for CentOS users
* Updated DMA engine
- DMA transfers from host to NetFPGA use the dedicated DMA bus between Spartan and Virtex
- Supports operation at both 125 MHz and 62.5 MHz (previous version only functioned at 125 MHz)
Minor new features and improvements:
* Kernel driver
- Checks added to prevent ioctl access outside of NetFPGA address space
- Checks added to prevent ioctl calls prior to complete card initialization (crashes seen on some CentOS 5 systems)
- Register read/write functions exported to allow other kernel modules to use NetFPGA module
- Added tx packet/byte counters (bug #4)
- Kernel unloading/reloading fixed (bug #15 + unreported bug)
* nf2_download
- Verifies that the Virtex bitfile was compiled against the CPCI version currently loaded (bug #54)
* cpci_reprogram
- Added --bit option to specify the CPCI bitfile to download
* Selftest
- Updated to support new DMA code
- Register addresses reassigned
* Utilities
- Added nf2_info tool (lib/C/tools/nf2_info) to display info in the device_id module
- Added sram_dump tool (lib/scripts/sram_dump) to dump the contents of SRAM
* Perl libraries
- Libraries restructed slightly to allow use in other projects (external interfaces should remain unchanged)
* Compatibility
- Minor changes to improve compatibility with non-supported Linux distributions
* Projects
- Project specific C/Perl register defines will be built when a local Verilog register defines exists
Version 1.1 beta
(29 Feb, 2008)
Minor new features and improvements:
* CentOS 5 compatibility
- Reference tests pass on CentOS 5.1 system
Version 1.0 beta
(12 Dec, 2007)
Initial release